The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition

Chapter 4

Architecture

Abstract

This chapter covers the details of the ARMv6-M architecture, the processor architecture on which Cortex^®-M0 and Cortex-M0+ processors are based on. The topics included the programmer's model, overview, and features of the memory system, interrupt handling, debug feature, and the start-up sequence of the Cortex-M processors.

Keywords

ARMv6-M architecture; Core's registers; Debug features overview; Exceptions and interrupts; Memory system; Nested Vectored Interrupt Controller (NVIC); Operation modes and states; Programmer's model; Reset sequence; Special registers; Stack memory

4.1. Overview of ARMv6-M Architecture

4.1.1. What Architecture Means

The ARM^® Cortex^®-M0 and Cortex-M0+ Processors are both based on the ARMv6-M ...