System Control and Low-Power Features
This chapter introduces a group of memory-mapped registers inside the System Control Space of the Cortex®-M0/Cortex-M0+ processors, including their usages like vector table relocation and self-reset. It then covers the low-power features of the Cortex-M0 and Cortex-M0+ processors such as sleep modes and the optional Wake-up Interrupt Controller.
KeywordsRegisters in SCB; Self-reset; Send-event-on-pend; Sleep mode; Sleep-on-exit; System control block (SCB); Vector table relocation; Wake-up interrupt controller (WIC)
9.1. Brief Introduction of System Control Registers
Inside the System Control Space (SCS) address range (0xE000E000 to 0xE000EFFF), there are a number of control registers built-in ...
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