Appendix A
Instruction Set Quick Reference
A.1. List of Instructions
The instructions supported on the ARM® Cortex®-M0 and Cortex-M0+ processors are listed in Table A.1.
Table A.1
Instruction set summary
| Syntax (Unified Assembly Language) | Description |
| ADCS <Rd>, <Rm> | ADD with Carry and update APSR |
| ADDS <Rd>, <Rn>, <Rm> | ADD registers and update APSR |
| ADDS <Rd>, <Rn>, #immed3 | ADD register and a 3-bit immediate value |
| ADDS <Rd>, #immed8 | ADD register and an 8-bit immediate value |
| ADD <Rd>, <Rm> | ADD two registers without update APSR |
| ADD <Rd>, SP, <Rd> | ADD the stack pointer to a register |
| ADD SP, <Rm> | ADD a register to the stack pointer |
| ADD <Rd>, SP, #immed8 | ADD stack pointer with an immediate value. Rd = SP + ZeroExtend(#immed8 <<2). |
| ADD SP, SP, #immed7 | ADD an immediate value ... |
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