Appendix D

NVIC, SCB, and SysTick Registers Quick Reference

D.1. NVIC Register Summary

Table D.1 listed the NVIC registers for interrupt control functions.

Table D.1

Summary of NVIC registers for interrupt control

AddressNameCMSIS symbolFull name
0xE000E100ISERNVIC-> ISERInterrupt Set Enable Register
0xE000E180ICERNVIC-> ICERInterrupt Clear Enable Register
0xE000E200ISPRNVIC-> ISPRInterrupt Set Pending Register
0xE000E280ISCPRNVIC-> ISPRInterrupt Clear Pending Register
0xE000E400IPR0-7NVIC-> IPR[0] to NVIC-> IPR[7]Interrupt Priority Register


D.1.1. Interrupt Set Enable Register (NVIC-> ISER)

In general, for enabling an interrupt with a CMSIS compliant device ...

Get The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.