book

The Designer's Guide to the Cortex-M Processor Family

by Trevor Martin

March 2013

Intermediate to advanced

336 pages

7h 41m

English

Newnes

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Cortex ProfilesCortex-M3Advanced Architectural FeaturesCortex-M0Cortex-M0+Cortex-M4DSP Instructions

IntroductionKeil Microcontroller Development KitThe Tutorial ExercisesInstallationExercise Building a First ProgramThe Blinky ProjectProject ConfigurationHardware Debug
IntroductionCortex-M Instruction SetProgrammer’s Model and CPU RegistersProgram Status RegisterQ Bit and Saturated Math InstructionsInterrupts and Multicycle InstructionsConditional Execution—IF THEN BlocksExercise: Saturated Math and Conditional ExecutionCortex-M Memory Map and BussesWrite BufferMemory Barrier InstructionsSystem Control BlockBit ManipulationExercise: Bit BandingDedicated Bit Manipulation InstructionsSystick TimerNested Vector Interrupt ControllerOperating ModesInterrupt Handling—EntryInterrupt Handling—ExitInterrupt Handling—Exit: Important!Exercise: Systick InterruptCortex-M Processor ExceptionsPriority and PreemptionGroups and SubgroupsRun Time Priority ControlException ModelExercise: Working with Multiple InterruptsBootloader SupportExercise: BootloaderPower ManagementMoving from the Cortex-M3Cortex-M4Cortex-M0Cortex-M0+
IntroductionCMSIS SpecificationsCMSIS CoreCMSIS RTOSCMSIS DSPCMSIS SVD and DAPFoundations of CMSISCoding RulesMISRA CCMSIS Core StructureStartup CodeSystem CodeDevice Header FileCMSIS Core Header FilesInterrupts and ExceptionsExercise: CMSIS and User Code ComparisonCMSIS Core Register AccessCMSIS Core CPU Intrinsic InstructionsExercise: Intrinsic Bit ManipulationCMSIS SIMD IntrinsicsCMSIS Core Debug FunctionsExercise: Simple ITM
IntroductionCortex Processor Operating ModesExercise: Stack ConfigurationSupervisor CallExercise: SVCPend_SVC ExceptionExample: Pend_SVCInterprocessor EventsExclusive AccessExercise: Exclusive AccessMemory Protection UnitConfiguring the MPUExercise: MPU ConfigurationMPU SubregionsMPU LimitationsAHB Lite Bus Interface
IntroductionGetting StartedSetting Up a ProjectFirst Steps with CMSIS RTOSThreadsStarting the RTOSExercise: A First CMSIS RTOS ProjectCreating ThreadsExercise: Creating and Managing ThreadsThread Management and PriorityExercise: Creating and Managing Threads IIMultiple InstancesExercise: Multiple Thread InstancesBuild the Code and Start the DebuggerTime ManagementTime DelayWaiting for an EventExercise: Time ManagementVirtual TimersExercise: Virtual TimerIdle DemonExercise Idle ThreadInterthread CommunicationExercise: SignalsExercise: Interrupt SignalExercise: CMSIS RTX and SVC ExceptionsExercise: Semaphore SignalingExercise: RendezvousExercise: Semaphore BarrierMessage QueueExercise: Message QueueMemory PoolMail QueueExercise: Mailbox
IntroductionCortex-M4 Hardware Floating Point UnitFPU IntegrationFPU RegistersEnabling the FPUExceptions and the FPUUsing the FPUExercise: Floating Point UnitCortex-M4 DSP and SIMD InstructionsExercise: SIMD InstructionsExercise: Optimizing DSP AlgorithmsThe CMSIS DSP LibraryCMSIS DSP Library FunctionsExercise: Using the LibraryDSP Data Processing TechniquesExercise: FIR Filter with Block ProcessingFixed Point DSP with Q NumbersExercise: Fixed Point FFTDesigning for Real-Time ProcessingBuffering Techniques: The Double or Circular BufferBuffering Techniques: FIFO Message QueueBalancing the LoadExercise: RTX IIRShouldering the Load, the Direct Memory Access Controller
IntroductionCoreSight HardwareDebugger HardwareCoreSight Debug ArchitectureExercise: CoreSight DebugHardware ConfigurationSoftware ConfigurationDebug LimitationsInstrumentation TraceExercise: Setting Up the ITMSoftware Testing Using the ITM with RTX RTOSError TaskSoftware Test TaskExercise: Software Testing with the ITMInstruction Trace with the ETMExercise: Using the ETM TraceSystem Control Block Debug SupportTracking FaultsExercise: Processor Fault ExceptionsCMSIS SVDExercise: CMSIS SVDCMSIS DAPCortex-M0+ MTBExercise: MTBDebug Features Summary
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Content preview from The Designer's Guide to the Cortex-M Processor Family

Chapter 3

Cortex-M Architecture

Introduction

In this chapter, we will take a closer look at the Cortex-M processor architecture. The bulk of this chapter will concentrate on the Cortex-M3 processor. Once we have a firm understanding of the Cortex-M3, we will look at the key differences in the Cortex-M0, M0+, and M4. There are a number of exercises throughout the chapter. These exercises will give you a deeper understanding of each topic and can be used as a reference when developing your own code.

Cortex-M Instruction Set

As we described in Chapter 1, the Cortex-M processors are Reduced Instruction Set Computer (RISC)-based processors and as such have a small instruction set. The Cortex-M0 has just 56 instructions, the Cortex-M3 has 74, and the ...