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The Designer's Guide to VHDL, 3rd Edition

Name: The Designer's Guide to VHDL, 3rd Edition
Author: Peter J. Ashenden
ISBN: 9780080568850

by Peter J. Ashenden

October 2010

Intermediate to advanced

936 pages

24h 27m

English

Morgan Kaufmann

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Copyright
Dedication
Preface
Structure of the BookChanges in the Second and Third EditionsResources for Help and InformationAcknowledgments
1. Fundamental Concepts
1.1. Modeling Digital Systems1.2. Domains and Levels of Modeling1.2.1. Modeling Example1.3. Modeling Languages1.4. VHDL Modeling Concepts1.4.1. Elements of Behavior1.4.2. Elements of Structure1.4.3. Mixed Structural and Behavioral Models1.4.4. Test Benches1.4.5. Analysis, Elaboration and Execution1.5. Learning a New Language: Lexical Elements and Syntax1.5.1. Lexical ElementsCommentsIdentifiersReserved WordsSpecial SymbolsNumbersCharactersStringsBit Strings1.5.2. Syntax DescriptionsExercises
2. Scalar Data Types and Operations
2.1. Constants and Variables2.1.1. Constant and Variable Declarations2.1.2. Variable Assignment2.2. Scalar Types2.2.1. Type Declarations2.2.2. Integer Types2.2.3. Floating-Point Types2.2.4. Physical TypesTime2.2.5. Enumeration TypesCharactersBooleansBitsStandard LogicCondition Conversion2.3. Type Classification2.3.1. Subtypes2.3.2. Type Qualification2.3.3. Type Conversion2.4. Attributes of Scalar Types2.5. Expressions and Predefined OperationsExercises
3. Sequential Statements
3.1. If Statements3.1.1. Conditional Variable Assignments3.2. Case Statements3.2.1. Selected Variable Assignments3.3. Null Statements3.4. Loop Statements3.4.1. Exit Statements3.4.2. Next Statements3.4.3. While Loops3.4.4. For Loops3.4.5. Summary of Loop Statements3.5. Assertion and Report StatementsExercises
4. Composite Data Types and Operations
4.1. Arrays4.1.1. Multidimensional Arrays4.1.2. Array Aggregates4.1.3. Array Attributes4.2. Unconstrained Array Types4.2.1. Predefined Array TypesStringsBoolean Vectors, Integer Vectors, Real Vectors, and Time VectorsBit VectorsStandard-Logic ArraysString and Bit-String Literals4.2.2. Unconstrained Array Element Types4.2.3. Unconstrained Array Ports4.3. Array Operations and Referencing4.3.1. Logical Operators4.3.2. Shift Operators4.3.3. Relational OperatorsMaximum and Minimum Operations4.3.4. The Concatenation Operator4.3.5. To_String Operations4.3.6. Array Slices4.3.7. Array Type Conversions4.3.8. Arrays in Case Statements4.3.9. Matching Case StatementsMatching Selected Variable Assignments4.4. Records4.4.1. Record Aggregates4.4.2. Unconstrained Record Element TypesExercises
5. Basic Modeling Constructs
5.1. Entity Declarations and Architecture Bodies5.1.1. Concurrent Statements5.1.2. Signal Declarations5.2. Behavioral Descriptions5.2.1. Signal AssignmentConditional Signal AssignmentsSelected Signal Assignments5.2.2. Signal Attributes5.2.3. Wait Statements5.2.4. Delta Delays5.2.5. Transport and Inertial Delay Mechanisms5.2.6. Process Statements5.2.7. Concurrent Signal Assignment StatementsConcurrent Simple Signal AssignmentsConcurrent Conditional Signal AssignmentConcurrent Selected Signal Assignments5.2.8. Concurrent Assertion Statements5.2.9. Entities and Passive Processes5.3. Structural Descriptions5.4. Design Processing5.4.1. Analysis5.4.2. Design Libraries and ContextsContext Declarations5.4.3. Elaboration5.4.4. ExecutionExercises
6. Subprograms
6.1. Procedures6.1.1. Return Statement in a Procedure6.2. Procedure Parameters6.2.1. Signal Parameters6.2.2. Default Values6.2.3. Unconstrained Array Parameters6.2.4. Summary of Procedure Parameters6.3. Concurrent Procedure Call Statements6.4. Functions6.4.1. Functional Modeling6.4.2. Pure and Impure Functions6.4.3. The Function now6.5. Overloading6.5.1. Overloading Operator Symbols6.6. Visibility of DeclarationsExercises
7. Packages and Use Clauses
7.1. Package Declarations7.1.1. Subprograms in Package Declarations7.1.2. Constants in Package Declarations7.2. Package Bodies7.2.1. Local Packages7.3. Use Clauses7.3.1. Visibility of Used DeclarationsExercises
8. Resolved Signals
8.1. Basic Resolved Signals8.1.1. Composite Resolved Subtypes8.1.2. Summary of Resolved Subtypes8.1.3. IEEE std_logic_1164 Resolved Subtypes8.2. Resolved Signals, Ports, and Parameters8.2.1. Resolved Ports8.2.2. Driving Value Attribute8.2.3. Resolved Signal ParametersExercises

9. Predefined and Standard Packages
9.1. The Predefined Packages standard and env9.2. IEEE Standard Packages9.2.1. Standard VHDL Mathematical PackagesReal Number Mathematical PackageComplex Number Mathematical Package9.2.2. The std_logic_1164 Multivalue Logic System9.2.3. Standard Integer Numeric Packages9.2.4. Standard Fixed-Point Packages9.2.5. Standard Floating-Point Packages9.2.6. Package SummaryOperator Overloading SummaryConversion Function SummaryStrength Reduction Function SummaryExercises
10. Case Study: A Pipelined Multiplier Accumulator
10.1. Algorithm Outline10.2. A Behavioral Model10.2.1. Testing the Behavioral Model10.3. A Register-Transfer-Level Model10.3.1. Testing the Register-Transfer-Level ModelExercises
11. Aliases
11.1. Aliases for Data Objects11.2. Aliases for Non-Data ItemsExercises
12. Generics
12.1. Generic Constants12.2. Generic Types12.3. Generic Lists in Packages12.3.1. Local Packages12.3.2. Abstract Data Types Using Packages12.4. Generic Lists in Subprograms12.5. Generic Subprograms12.6. Generic PackagesExercises
13. Components and Configurations
13.1. Components13.1.1. Component Declarations13.1.2. Component Instantiation13.1.3. Packaging Components13.2. Configuring Component Instances13.2.1. Basic Configuration Declarations13.2.2. Configuring Multiple Levels of Hierarchy13.2.3. Direct Instantiation of Configured Entities13.2.4. Generic and Port Maps in Configurations13.2.5. Deferred Component Binding13.3. Configuration Specifications13.3.1. Incremental BindingExercises
14. Generate Statements
14.1. Generating Iterative Structures14.2. Conditionally Generating Structures14.2.1. Recursive Structures14.3. Configuration of Generate StatementsExercises
15. Access Types
15.1. Access Types15.1.1. Access Type Declarations and Allocators15.1.2. Assignment and Equality of Access Values15.1.3. Access Types for Records and Arrays15.2. Linked Data Structures15.2.1. Deallocation and Storage Management15.3. An Ordered-Dictionary ADT Using Access TypesExercises
16. Files and Input/Output
16.1. Files16.1.1. File Declarations16.1.2. Reading from Files16.1.3. Writing to Files16.1.4. Files Declared in Subprograms16.1.5. Explicit Open and Close Operations16.1.6. File Parameters in Subprograms16.1.7. Portability of Files16.2. The Package Textio16.2.1. Textio Read Operations16.2.2. Textio Write Operations16.2.3. Reading and Writing Other TypesStandard Package Read and Write OperationsExercises
17. Case Study: A Package for Memories
17.1. The Memories Package17.2. Using the Memories Package17.2.1. Common Address and Data ConversionsExercises
18. Test Bench and Verification Features
18.1. External Names18.2. Force and Release Assignments18.3. Embedded PSL in VHDLExercises
19. Shared Variables and Protected Types
19.1. Shared Variables and Mutual Exclusion19.2. Uninstantiated Methods in Protected TypesExercises
20. Attributes and Groups
20.1. Predefined Attributes20.1.1. Attributes of Scalar Types20.1.2. Attributes of Array Types and Objects20.1.3. Attributes Giving Types20.1.4. Attributes of Signals20.1.5. Attributes of Named Items20.2. User-Defined Attributes20.2.1. Attribute Declarations20.2.2. Attribute Specifications20.3. GroupsExercises
21. Design for Synthesis
21.1. Synthesizable Subsets21.2. Use of Data Types21.2.1. Scalar Types21.2.2. Composite and Other Types21.3. Interpretation of Standard Logic Values21.4. Modeling Combinational Logic21.5. Modeling Sequential Logic21.5.1. Modeling Edge-Triggered Logic21.5.2. Level-Sensitive Logic and Inferring Storage21.5.3. Modeling State Machines21.6. Modeling Memories21.7. Synthesis Attributes21.8. MetacommentsExercises
22. Case Study: System Design Using the Gumnut Core
22.1. Overview of the Gumnut22.1.1. Instruction Set Architecture22.1.2. External InterfaceThe Gumnut Entity DeclarationInstruction and Data Memories22.2. A Behavioral Model22.2.1. The Gumnut Definitions Package22.2.2. The Gumnut Behavioral Architecture BodyOverview of the InterpreterResetting the InterpreterAcknowledging an InterruptFetching an InstructionPerforming an Arithmetic/Logical OperationPerforming a Shift OperationPerforming a Memory-I/O InstructionPerforming a Branch InstructionPerforming a Jump InstructionPerforming a Miscellaneous Instruction22.2.3. Verifying the Behavioral Model22.3. A Register-Transfer-Level Model22.3.1. The Architecture Body22.3.2. Verifying the RTL Model22.4. A Digital Alarm Clock22.4.1. System Design22.4.2. Synthesizing and Implementing the Alarm ClockExercises
23. Miscellaneous Topics
23.1. Guards and Blocks23.1.1. Guarded Signals and DisconnectionThe Driving AttributeGuarded PortsGuarded Signal Parameters23.1.2. Blocks and Guarded Signal AssignmentExplicit Guard SignalsDisconnection Specifications23.1.3. Using Blocks for Structural ModularityExternal Names and BlocksGenerics and Ports in BlocksConfiguring Designs with Blocks23.2. IP Encryption23.2.1. Key Exchange23.3. VHDL Procedural Interface (VHPI)23.3.1. Direct Binding23.3.2. Tabular Registration and Indirect Binding23.3.3. Registration of Applications and Libraries23.4. Postponed Processes23.5. Conversion Functions in Association Lists23.6. Linkage PortsExercises
A. Standard Packages
A.1. The Predefined Package standardA.2. The Predefined Package envA.3. The Predefined Package textioA.4. Standard VHDL Mathematical PackagesA.4.1. The math_real PackageA.4.2. The math_complex PackageA.5. The std_logic_1164 Multivalue Logic System PackageA.6. Standard Integer Numeric PackagesA.6.1. The numeric_bit PackageA.6.2. The numeric_std PackageA.6.3. The numeric_bit_unsigned PackageA.6.4. The numeric_std_unsigned PackageA.7. Standard Fixed-Point PackagesA.7.1. The fixed_float_types PackageA.7.2. The fixed_generic_pkg PackageA.7.3. The fixed_pkg PackageA.8. Standard Floating-Point PackagesA.8.1. The float_generic_pkg PackageA.8.2. The float_pkg Package
B. VHDL Syntax
B.1. Design FileB.2. Library Unit DeclarationsB.3. Declarations and SpecificationsB.4. Type DefinitionsB.5. Concurrent StatementsB.6. Sequential StatementsB.7. Interfaces and AssociationsB.8. Expressions and Names
C. Answers to Exercises
Chapter 1Chapter 2Chapter 3Chapter 4Chapter 5Chapter 6Chapter 7Chapter 8Chapter 9Chapter 10Chapter 11Chapter 12Chapter 13Chapter 14Chapter 15Chapter 16Chapter 17Chapter 18Chapter 19Chapter 20Chapter 21Chapter 22Chapter 23
References

Content preview from The Designer's Guide to VHDL, 3rd Edition

Chapter 18. Test Bench and Verification Features

One of the characteristics of VHDL is that it allows a verification test bench to be written in the same language as the design to be verified. We have seen this in numerous examples in earlier chapters. We include the design to be verified as a component instance in a test bench model. We write VHDL statements to apply sequences of test values to the input ports of the design, and verify that the design produces the expected output values. However, some aspects of the language that we have seen so far make it hard to verify designs. The visibility rules are an example. They are intended to help us manage name spaces in complex designs by enforcing abstraction of interfaces and hiding of internal ...

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The Designer's Guide to VHDL, 2nd Edition

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The Designer's Guide to VHDL, 3rd Edition

by Peter J. Ashenden

Chapter 18. Test Bench and Verification Features

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