Chapter 18. Test Bench and Verification Features

One of the characteristics of VHDL is that it allows a verification test bench to be written in the same language as the design to be verified. We have seen this in numerous examples in earlier chapters. We include the design to be verified as a component instance in a test bench model. We write VHDL statements to apply sequences of test values to the input ports of the design, and verify that the design produces the expected output values. However, some aspects of the language that we have seen so far make it hard to verify designs. The visibility rules are an example. They are intended to help us manage name spaces in complex designs by enforcing abstraction of interfaces and hiding of internal ...

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