Interconnect Noise Analysis and Optimization in Deep Submicron Technology
Mohamed Elgamel and Magdy Bayoumi, The Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, Louisiana, USA
8.1. Introduction
8.2. Interconnect Noise Models
8.2.1. Lumped Interconnect Model
8.2.2. Distributed Interconnect Model
8.2.3. Interconnect Modeling Issues
8.3. Noise Minimization Techniques
8.3.1. Buffer Insertion
8.3.2. Wire Sizing
8.3.3. Wire Spacing
8.3.4. Shield Insertion
8.3.5. Network Ordering
8.4. Interconnect Noise in Early Design Stages
8.5. Case Study Pentium 4
8.5.1. Interconnect Delay and Crosscapacitance Scaling
8.5.2. Wire and Repeater Design Methodology for the Pentium 4 Processor
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