book

The ESD Handbook

Name: The ESD Handbook
Author: Steven H. Voldman
ISBN: 9781119965176

by Steven H. Voldman

April 2021

Intermediate to advanced

1168 pages

37h 19m

English

Wiley

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Cover
Title Page
Copyright
Dedication
About the Author
Acknowledgements
1 ESD, EOS, EMI, EMC, and Latchup
1.1 Electrostatic Discharge (ESD)1.2 Human Body Model (HBM)1.3 Machine Model (MM)1.4 Cassette Model1.5 Charged Device Model (CDM)1.6 Transmission Line Pulse (TLP)1.7 Very Fast Transmission Line Pulse (VF-TLP)1.8 Electrical Overstress (EOS)1.9 Electrical Overstress (EOS)1.10 EOS Sources – Lightning1.11 EOS Sources – Electromagnetic Pulse (EMP)1.12 EOS Sources – Machinery1.13 EOS Sources – Power Distribution1.14 EOS Sources – Switches, Relays, and Coils1.15 EOS Design Flow and Product Definition1.16 EOS Sources – Design Issues1.17 Electromagnetic Interference (EMI)1.18 Electromagnetic Compatibility (EMC)1.19 LatchupQuestions and Answers1.20 Summary and Closing CommentsReferences
2 ESD in Manufacturing
2.1 Flooring2.2 Work Surfaces2.3 Garments2.4 Wrist Straps2.5 Shoes – Footwear2.6 Ionization2.7 Clean Rooms2.8 Carts2.9 Shipping Tubes2.10 Trays2.11 Measurements2.12 Verification2.13 Audit2.14 Triboelectric Charging – How Does it Happen?2.15 Conductors, Semiconductors, and Insulators2.16 Static Dissipative Materials2.17 ESD and Materials2.18 Electrification and Coulomb’s Law2.19 Electromagnetism and Electrodynamics2.20 Electrical Breakdown2.21 Electro-Quasistatics and Magnetoquasistatics2.22 Electrodynamics and Maxwell’s Equations2.23 Electrostatic Discharge (ESD)2.24 Electromagnetic Compatibility (EMC)2.25 Electromagnetic Interference (EMI)2.26 Fundamentals of Manufacturing and Electrostatics2.27 Materials, Tooling, Human Factors, and Electrostatic Discharge2.28 Materials and Human-induced Electric Fields2.29 Manufacturing Environment and Tooling2.30 Manufacturing Equipment and ESD Manufacturing Problems2.31 Manufacturing Materials2.32 Measurement and Test Equipment2.33 Manufacturing Testing for Compliance2.34 Grounding and Bonding Systems2.35 Work Surfaces2.36 Wrist Straps2.37 Constant Monitors2.38 Footwear2.39 Floors2.40 Personnel Grounding with Garments2.41 Garments2.42 Air Ionization2.43 Seating2.44 Packaging and Shipping2.45 Trays2.46 ESD Identification2.47 ESD Program Auditing2.48 ESD On-Chip Protection2.49 ESD, EOS, EMI, EMC, and Latchup2.50 Manufacturing Electrical Overstress (EOS)2.51 EMI2.52 EMC2.53 Summary and Closing CommentsReferences
3 ESD Standards
3.1 Factory – Flooring3.2 Factory – Resistance Measurement of Materials3.3 JEDEC3.4 International Electro-Technical Commission (IEC)3.5 IEEE3.6 Department of Defense (DOD)3.7 Military Standards3.8 SAE3.9 Summary and Closing CommentsQuestions and AnswersReferences
4 ESD Testing
4.1 Electrostatic Discharge (ESD) Testing4.2 ESD Models4.3 HBM Test System4.4 HBM Two-pin Test System4.5 Machine Model (MM)4.6 Small Charge Model (SCM)4.7 Small Charge Model Source4.8 CDM Pulse Waveform4.9 HMM Equivalent Circuit4.10 HMM Test Equipment4.11 HMM Test Configuration4.12 HMM Fixture Board4.13 Transmission Line Pulse (TLP)4.14 TLP Test Systems4.15 IEC 61000-4-24.16 Equivalent Circuit4.17 Test Equipment4.18 Cable Discharge Event (CDE)4.19 CDE Pulse Waveform4.20 Equivalent Circuit4.21 Commercial Test Systems4.22 Systems Electromagnetic Interference (EMI)4.23 Electromagnetic Compatibility (EMC)4.24 Electrical Overstress (EOS)4.25 Latchup4.26 Electrical Overstress (EOS)4.27 EOS Sources – Lightning4.28 EOS Sources – Electromagnetic Pulse (EMP)4.29 Electromagnetic Compatibility4.30 Summary and Closing CommentsReferences

5 ESD Device Physics
5.1 Electro-thermal Instability5.2 Stable System5.3 Unstable System5.4 Differential Relation of Voltage and Current5.5 Time Constant Hierarchy5.6 Thermal Physics Time Constants5.7 Adiabatic, Thermal Diffusion Time Scale and Steady State5.8 Electro-quasistatic and Magnetoquasistatics5.9 Electrical Instability5.10 Thermal Physics Time Constants5.11 Adiabatic, Thermal Diffusion Time Scale and Steady State5.12 Electrical Instability and Breakdown5.13 Spatial Instability and Electro-thermal Current Constriction5.14 Equipotential Surface5.15 Heat Flow5.16 Conservation of Heat5.17 Electric Potential and Temperature Gradient5.18 Electric Energy, Resistivity, and Thermal Conductivity5.19 Breakdown5.20 Electron Current Continuity Relationship5.21 Air Breakdown and Peak Currents5.22 Electro-thermal Instability5.23 Mathematical Methods – Green’s Function and Method of Images5.24 Mathematical Methods – Green’s Function and Method of Images5.25 Mathematical Methods – Integral Transforms of the Heat Conduction Equation5.26 Flux Potential Transfer Relations Matrix Methodology5.27 Heat Equation Variable Conductivity5.28 Mathematical Methods – Boltzmann Transformation5.29 Mathematical Methods – The Duhamel Formulation5.30 Spherical Source Tasca Model5.31 Wunsch–Bell Model5.32 The Smith and Littau Model5.33 The Arkihpov–Astvatsaturyan–Godovosyn–Rudenko Model5.34 The Vlasov–Sinkevitch Model5.35 The Dwyer, Franklin and Campbell Model5.36 Negative Differential Resistor and Resistor Ballasting5.37 Ash Model – Nonlinear Failure Power Thresholds5.38 Statistical Models for ESD Prediction5.39 Summary and Closing CommentsReferences
6 ESD Events and Protection Circuits
6.1 Human Body Model (HBM)6.2 Machine Model (MM)6.3 Charged Device Model6.4 Human Metal Model (HMM)6.5 IEC 61000-4-2 History6.6 IEC 61000-4-56.7 Cable Discharge Event (CDE)6.8 CDM ScopeReferences
7 ESD Failure Mechanism
7.1 Tables of CMOS ESD Failure Mechanisms7.2 LOCOS Isolation-Defined CMOS7.3 LOCOS-bound Thick Oxide MOSFET7.4 LOCOS-Bound Structures7.5 Shallow Trench Isolation (STI)7.6 STI Pull-down ESD Failure Mechanism7.7 STI Pull-Down and Gate Wrap-Around7.8 MOSFETs7.9 LOCOS-bound Thick Oxide MOSFET7.10 Bipolar Transistor Devices7.11 Silicide Blocked N-diffusion Resistors7.12 Silicon Germanium ESD Failure Mechanisms7.13 Silicon Germanium Carbon ESD Failure Mechanisms7.14 Gallium Arsenide Technology ESD Failure Mechanisms7.15 Indium Gallium Arsenide ESD Failure Mechanisms7.16 Micro Electromechanical (MEM) Systems7.17 Micro-mirror Array Failures7.18 EOS Bond Pad and Interconnect Failure7.19 Summary and Closing Comments References
8 ESD Design Synthesis
8.1 ESD Design Synthesis and Architecture Flow8.2 ESD Design – the Signal Path and the Alternate Current Path8.3 ESD Electrical Circuit and Schematic Architecture Concepts8.4 The Ideal ESD Network8.5 Mapping Semiconductor Chips and ESD Designs8.6 Mapping across Semiconductor Fabricators8.7 ESD Design Mapping across Technology Generations8.8 ESD Networks, Sequencing, and Chip Architecture8.9 ESD Layout and Floorplan-related Concepts8.10 ESD Architecture and Floor-planning8.11 Digital and Analog CMOS Architecture8.12 Digital and Analog Floorplan – Placement of Analog Circuits8.13 Mixed-signal Architecture – Digital, Analog, and RF Architecture8.14 Summary and Closing CommentsQuestionsReferences
9 On-chip ESD Protection Circuits – Input Circuitry
9.1 Receivers and ESD9.2 Receivers and Receiver Delay Time9.3 ESD Loading Effect on Receiver Performance9.4 Receivers and HBM9.5 Receivers and CDM9.6 Receivers and Receiver Evolution9.7 Receiver Circuits with Half-pass Transmission Gate9.8 Receiver with Full-pass Transmission Gate9.9 Receiver, Half-pass Transmission Gate, and Keeper Network9.10 Receiver, Half-pass Transmission Gate, and the Modified Keeper Network9.11 Receiver Circuits with Pseudo-zero VT Half-pass Transmission Gates9.12 Receiver with Zero VT Transmission Gate9.13 Receiver Circuits with Bleed Transistors9.14 Receiver Circuits with Test Functions9.15 Receiver with Schmitt Trigger Feedback Network9.16 Bipolar Transistor Receivers9.17 CMOS Differential Receiver with Analog Layout Concepts9.18 CMOS Differential Receiver Capacitance Loading9.19 CMOS Differential Receiver ESD Mismatch9.20 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout9.21 Analog Differential Pair Common Centroid Design Layout – Signal-Pin to Signal-Pin and Parasitic ESD Elements9.22 Off-chip Drivers (OCD)9.23 Off-chip Driver I/O Standards and ESD9.24 Off-chip Driver (OCD) ESD Design Basics9.25 Off-chip Drivers (OCD): Mixed Voltage Interface9.26 Off-chip Drivers (OCD): Self-bias Well OCD Networks 9.27 Self-bias Well Off-chip Driver (OCD) Networks9.28 ESD Protection Networks for Self-bias Well OCD Networks9.29 Programmable Impedance Off-chip Driver (OCD) Network9.30 ESD Input Protection Networks for Programmable Impedance Off-chip Drivers9.31 Universal Off-chip Drivers9.32 Gate Array Off-chip Driver Design9.33 Gate Array OCD Design – Impedance Matching of Unused Elements9.34 OCD ESD Design – Power Rails Over Multi-finger MOSFETs9.35 Off-chip Driver: Gate-modulated MOSFET ESD Network9.36 Off-chip Driver Simplified Gate Modulated Network9.37 Off-chip Drivers ESD Design: Integration of Coupling and Ballasting Techniques9.38 Ballasting and Coupling9.39 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with Diode9.40 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with a MOSFET9.41 Gate-coupled Domino Resistor-ballasted MOSFET9.42 Substrate-modulated Resistor Ballasted MOSFET9.43 Summary and Closing CommentsProblems References
10 On-Chip ESD Protection Circuits – ESD Power Clamps
10.1 ESD Power Clamps10.2 ESD Power Clamp Design Practices10.3 Current Loops10.4 Impedance10.5 Segmentation10.6 Voltage Limitations10.7 Latchup10.8 ESD Power Clamp Circuits10.9 Classification of ESD Power Clamps10.10 Master-Slave ESD Power Clamps10.11 Trigger Networks10.12 ESD Power Clamp Characteristics and Issues10.13 Design Synthesis of ESD Power Clamp – Key Design Parameters10.14 Design Synthesis of ESD Power Clamps Trigger Networks10.15 Transient Response Frequency Trigger Element and the ESD Frequency Window10.16 ESD Power Clamp Frequency Design Window10.17 Design Synthesis of ESD Power Clamp – Voltage Triggered ESD Trigger Elements10.18 Design Synthesis of ESD Power Clamp – The ESD Power Clamp Shunting Element10.19 ESD Power Clamp Trigger Condition vs. Shunt Failure10.20 ESD Clamp Element – Width Scaling10.21 ESD Clamp Element – On-resistance10.22 ESD Clamp Element – Safe Operating Area (SOA)10.23 ESD Power Clamp Issues10.24 ESD Power Clamp Issues – Power-up and Power-down10.25 ESD Power Clamp Issues – False Triggering10.26 ESD Power Clamp Issues – Pre-charging10.27 ESD Power Clamp Issues – Post-charging10.28 ESD Power Clamp Design10.29 ESD Power Clamp Design Synthesis – Forward Bias Triggered ESD Power Clamps10.30 Series Stacked RC-triggered ESD Power Clamps10.31 Triple Well Diode String ESD Power Clamp10.32 Bipolar ESD Power Clamps10.33 ESD Power Clamp Design Synthesis – Bipolar ESD Power Clamps10.34 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance-triggered10.35 Silicon Controlled Rectifier Power ClampsProblems References
11 ESD Architecture and Floor Planning
11.1 ESD Design Floor Plan11.2 Peripheral I/O Design11.3 Pad Limited Peripheral I/O Design Architecture11.4 Pad Limited Peripheral I/O Design Architecture – Staggered I/O11.5 Core Limited Peripheral I/O Design Architecture11.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture11.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners11.8 Lumped ESD Power Clamp in Peripheral I/O Design Architecture – Power Pads11.9 Lumped ESD Power Clamp in Peripheral I/O Design Architecture – Master/Slave ESD Power Clamp System11.10 Array I/O11.11 Array I/O Nibble Architecture11.12 Array I/O Pair Architecture11.13 Array I/O – Fully Distributed11.14 ESD Architecture – Dummy Bus Architecture11.15 ESD Architecture – Dummy VDD Bus11.16 ESD Architecture – Dummy Ground (VSS) Bus11.17 Native Voltage Power Supply Architecture11.18 Single Power Supply Architecture11.19 Mixed Voltage Architecture11.20 Mixed Voltage Architecture – Single Power Supply11.21 Mixed Voltage Architecture – Dual Power Supply11.22 Mixed Signal Architecture11.23 Digital and Analog Floor Plan – Placement of Analog Circuits11.24 Mixed Signal Architecture – Digital, Analog, and RF Architecture11.25 ESD Power Grid Design11.26 I/O to Core Guard Rings11.27 Within I/O Guard Rings11.28 ESD-to-I/O Off-Chip Driver (OCD) Guard Ring 11.29 Guard Rings and Computer Aided Design (CAD) Methods11.30 Summary and Closing CommentsReferences
12 ESD Digital Design
12.1 Fundamental Concepts of ESD Design12.2 Concepts of ESD Digital Design12.3 Device Response to External Events12.4 Alternative Current Loops12.5 Decoupling of Feedback Loops12.6 Decoupling of Power Rails12.7 Local and Global Distribution12.8 Usage of Parasitic Elements12.9 Unused Section of a Semiconductor Device, Circuit, or Chip Function12.10 Unused Corners12.11 Unused White Space12.12 Impedance Matching Between Floating and Non-floating Networks12.13 Unconnected Structures12.14 Symmetry12.15 Design Synthesis12.16 ESD, Latchup, and Noise12.17 Structures Under Bond Pads12.18 Summary and Closing Comments References
13 ESD Analog Design
13.1 Analog Design: Local Matching13.2 Analog Design: Global Matching13.3 Symmetry13.4 Analog Design – Local Matching13.5 Analog Design – Global Matching13.6 Common Centroid Design13.7 Common Centroid Arrays13.8 Interdigitation Design13.9 Common Centroid and Interdigitation Design13.10 Dummy Resistor Layout13.11 Thermoelectric Cancelation Layout13.12 Electrostatic Shield13.13 Interdigitated Resistors and ESD Parasitics13.14 Capacitor Element Design13.15 Inductor Element Design13.16 ESD Failure in Inductors13.17 Inductor Physical Variables13.18 Inductor Element Design13.19 Diode Design13.20 Analog ESD Circuits13.21 ESD MOSFETs13.22 Receivers13.23 CMOS Differential Receiver with Analog Layout Concepts13.24 Analog Differential Pair Common Centroid Design Layout – Signal-pin to Signal-pin and Parasitic ESD Elements 13.25 Summary and Closing CommentsReferences
14 ESD RF Design
14.1 Fundamental Concepts of ESD Design14.2 Fundamental Concepts of RF ESD Design14.3 RF CMOS Input Circuits14.4 RF CMOS Impedance Isolation LC Resonator ESD Networks14.5 RF CMOS LC-diode Networks Experimental Results14.6 RF CMOS LNA ESD Design – Low Resistance ESD Inductor and ESD Diode Clamping Elements in Π-configuration14.7 RF CMOS T-coil Inductor ESD Input Network14.8 RF CMOS Distributed ESD Networks14.9 RF CMOS Distributed ESD-RF Networks14.10 RF CMOS Distributed RF-ESD Networks Using Series Inductors and Dual-diode Shunts14.11 RF CMOS Distributed RF-ESD Networks Using Series Inductors and MOSFET Parallel Shunts14.12 RF CMOS Distributed ESD Networks – Transmission Lines and Co-planar Waveguides14.13 RF CMOS – ESD and RF LDMOS Power Technology14.14 Summary and Closing CommentsReferences
15 ESD Power Electronics Design
15.1 Reliability Technology Scaling and the Reliability Bathtub Curve15.2 Input Circuitry15.3 Summary and Closing CommentsReferences
16 ESD in Advanced CMOS
16.1 Interconnects and ESD16.2 Aluminum Interconnects16.3 Interconnects – Vias16.4 Interconnects – Wiring16.5 Junctions16.6 Titanium Silicide16.7 Shallow Trench Isolation16.8 LOCOS-bound ESD Structures16.9 LOCOS-bound p+/n-well Junction Diodes16.10 LOCOS-bound n+ Junction Diodes16.11 LOCOS-bound n-well/Substrate Diodes16.12 LOCOS-bound Lateral N-Well to N-Well Bipolar ESD Element16.13 LOCOS-bound Lateral N+ to N-well Bipolar ESD Element16.14 LOCOS-bound Lateral pnp Bipolar ESD Element16.15 LOCOS-bound Thick Oxide MOSFET ESD Element16.16 Shallow Trench Isolation16.17 STI-bound ESD Structures16.18 Substrate Modeling – Electrical and Thermal Discretization16.19 Heavily Doped Substrates16.20 Retrograde Wells and ESD Scaling16.21 Triple Well and Isolated MOSFET CMOS16.22 Summary and Closing CommentsReferences
17 ESD in Silicon on Insulator
17.1 Silicon on Insulator (SOI) Technologies17.2 Elimination of CMOS Latchup17.3 Lack of Vertical Bipolar Transistors17.4 Floating Gate Tie Downs17.5 Physical Separation of MOSFETs from the Bulk Substrate17.6 SOI ESD Design Fundamental Concepts17.7 SOI Lateral Diode Structure17.8 Transistors – Bulk versus SOI Technology17.9 SOI Buried Resistors (BR) Elements17.10 Dynamic Threshold MOS (DTMOS) SOI MOSFET 17.11 SOI P+ Body Contact Abutting n+ Drain17.12 Transmission Line Pulse (TLP) Testing of SOI Diode Designs17.13 SOI ESD with MOSFET Drain and Body Width Ratio Variation17.14 SOI Dual-Gate MOSFET Structure17.15 SOI ESD Design – Mixed Voltage T-Shape Layout Style17.16 SOI ESD Design: Double Diode Network17.17 Bulk to SOI ESD Design Remapping17.18 SOI ESD Diode Design Parameters17.19 SOI ESD Design in Mixed Voltage Interface Environments17.20 Comparison of Bulk with SOI ESD Results17.21 SOI ESD Design with Aluminum Interconnects17.22 SOI ESD Design with Copper Interconnects17.23 SOI ESD Design with Gate Circuitry17.24 Summary and Closing CommentsReferences
18 ESD in Analog Circuits
18.1 Analog Design Circuits18.2 Single-ended Receivers18.3 Schmitt Trigger Receivers18.4 Differential Receivers18.5 Comparators18.6 Current Sources18.7 Current Mirrors18.8 Widlar Current Mirror18.9 Wilson Current Mirror18.10 Voltage Regulators18.11 Buck Converters18.12 Boost Converters18.13 Buck-Boost Converters18.14 Cuk Converters18.15 Voltage Reference Circuits18.16 Brokaw Bandgap Voltage Reference18.17 Converters18.18 Analog-to-Digital Converter (ADC)18.19 Digital-to-Analog Converters (DAC)18.20 Oscillators18.21 Phase Lock Loop (PLL) Circuits18.22 Delay Locked Loop (DLL)18.23 Analog and ESD Design Synthesis18.24 Analog Chip Architecture – Separation of Analog Power from Digital Power, AVDD–DVDD 18.25 ESD Failure in Phase Lock Loop (PLL) and System Clock18.26 ESD Failure in Current Mirrors18.27 ESD Failure in Schmitt Trigger Receivers18.28 ESD Design Practice – Prevent ESD Failure in Schmitt Trigger18.29 Analog–Digital Architecture: Isolated Digital and Analog Domains18.30 ESD Protection Solution – Connectivity of AVDD-to-VDD 18.31 ESD Solution: Connectivity of AVSS-to-DVSS 18.32 Digital and Analog Domain with ESD Power Clamps18.33 Digital and Analog Domain with Master–Slave ESD Power Clamps18.34 High Voltage, Digital, and Analog Domain Floorplan18.35 Floor-planning of Digital and Analog18.36 Inter-domain Signal Lines ESD Failures18.37 Digital-to-Analog Signal Line ESD Failures18.38 Digital-to-Analog Core Spatial Isolation18.39 Digital-to-Analog Core Ground Coupling18.40 Digital-to-Analog Core Resistive Ground Coupling18.41 Digital-to-Analog Core Diode Ground Coupling18.42 Domain-to-Domain Signal Line ESD Networks18.43 Domain-to-Domain Third-party Coupling Networks18.44 Domain-to-Domain Cross-domain ESD Power Clamp18.45 Digital-to-Analog Domain Moat18.46 Analog and ESD Circuit Integration18.47 Integrated Body Ties18.48 Self-Protecting vs Non-self Protecting DesignsReferences
19 ESD in RF CMOS
19.1 CMOS and ESD19.2 RF CMOS19.3 RF CMOS and ESD19.4 RF CMOS ESD Failure Mechanisms19.5 RF CMOS – ESD Device Comparisons19.6 RF ESD Metrics19.7 Grounded Gate n-channel MOSFET versus STI Diode19.8 Silicon-controlled Rectifier19.9 SCR versus GGNMOS19.10 Shallow Trench Isolation and Polysilicon Gated Diodes19.11 RF ESD Design19.12 RF ESD Design Layout – Circular RF ESD Devices19.13 Disadvantage of RF ESD Circular Element19.14 RF ESD Design – ESD Wiring Design19.15 RF ESD Design – Loading Capacitance19.16 Metal Capacitance19.17 Analog Metal (AM)19.18 RF ESD Design Practices19.19 RF Passives – ESD and Schottky Barrier Diodes19.20 Schottky Barrier Diodes and Metallurgy19.21 Silicon Germanium Schottky Barrier Diodes19.22 Schottky Barrier RF ESD Design Practice19.23 RF Passives – ESD and Inductors19.24 Quality Factor, Q19.25 Incremental Model of an Inductor19.26 Inductor Coil Parameters19.27 RF Passives – ESD and Capacitors19.28 Capacitors and RF Applications19.29 Capacitors in ESD Networks19.30 Types of Radio Frequency Capacitors19.31 Metal-Oxide-Semiconductor and Metal-Insulator-Metal Capacitors19.32 Varactors and Hyper-abrupt Junction Varactor Capacitors19.33 Metal-ILD-Metal Capacitors19.34 Vertical Parallel Plate (VPP) Capacitors19.35 Tips: ESD RF Design Practices for Capacitors19.36 Summary and Closing CommentsProblemsReferences
20 ESD in Silicon Germanium
20.1 Heterojunctions Bipolar Transistors20.2 Silicon Germanium20.3 Silicon Germanium HBT Devices20.4 Silicon Germanium Device Structure20.5 Silicon Germanium Film Deposition20.6 Silicon Germanium Emitter–Base Region20.7 Silicon Germanium Physics20.8 Silicon Germanium Bandgap20.9 Silicon Germanium Intrinsic Temperature20.10 Position-dependent Silicon Germanium Profile20.11 Position-dependent Intrinsic Temperature20.12 SiGe Collector Current with Graded Germanium Concentration20.13 Silicon Germanium ESD and Time Constants20.14 Silicon Germanium Base Transit Time20.15 Silicon Germanium Breakdown Voltages20.16 Silicon Germanium ESD Measurements20.17 Silicon Germanium Collector-to-Emitter ESD Stress20.18 Transmission Line Pulse Testing of Silicon Germanium HBT20.19 Transmission Line Pulse (TLP) I-V Characteristic20.20 Wunsch–Bell Characteristic of Silicon Germanium HBT20.21 Comparison of Silicon Germanium HBT and Silicon BJT20.22 Wunsch–Bell Characteristic of SiGe HBT versus Si BJT20.23 Intrinsic Base Resistance in SiGe HBT20.24 SiGe HBT Electro-thermal HBM Simulation of Collector–Emitter Stress20.25 Silicon Germanium Transistor Emitter–Base Design20.26 Epitaxial-Base Hetero-Junction Bipolar Transistor (HBT) Emitter–Base Design20.27 Self-aligned Silicon Germanium HBT Device20.28 Non-Self Aligned Silicon Germanium HBT20.29 Emitter–Base Design RF Frequency Performance Metrics20.30 SiGe HBT Emitter–Base Resistance Model20.31 SiGe HBT Emitter–Base Design and Silicide Placement20.32 Silicide Material and ESD20.33 Titanium Silicide and ESD20.34 Cobalt Salicide20.35 Self-aligned (SA) Emitter Base Design20.36 Non-Self Aligned (NSA) Emitter Base Design20.37 Non-Self Aligned HBT Human Body Model (HBM) Step Stress20.38 Transmission Line Pulse (TLP) Step Stress20.39 RF Testing of SiGe HBT Emitter–Base Configuration20.40 Unity Current Gain Cutoff Frequency – Collector Current Plots20.41 fMAX and fT20.42 Electrothermal Simulation of Emitter–Base Stress20.43 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data20.44 Silicon Germanium HBT Multiple-emitter Study20.45 RF ESD Design Practice20.46 Silicon Germanium ESD Failure Mechanisms20.47 Summary and Closing CommentsReferences
21 ESD in Silicon Germanium Carbon
21.1 Heterojunctions and Silicon Germanium Carbon Technology21.2 Silicon Germanium Carbon21.3 Silicon Germanium Carbon Collector–Emitter ESD Measurements21.4 Silicon Germanium Transistor Emitter–Base Design21.5 Silicon Germanium Carbon – ESD-Induced S-Parameter Degradation 21.6 Silicon Germanium Carbon ESD Failure Mechanisms21.7 Summary and Closing CommentsReferences
22 ESD in GaAs
22.1 Gallium Arsenide Technology and ESD22.2 Gallium Arsenide Energy-to-Failure, and Power-to-Failure22.3 Gallium Arsenide ESD Failures in Active and Passive Elements22.4 Gallium Arsenide HBT Devices and ESD22.5 Gallium Arsenide HBT Device ESD Results22.6 Gallium Arsenide HBT Diode Strings22.7 Gallium Arsenide HBT-based Passive Elements22.8 GaAs HBT Base–Collector Varactor22.9 Gallium Arsenide Technology Table of Failure Mechanisms22.10 Application – GaAs Power Amplifier in a Cell Phone22.11 Summary and Closing CommentsQuestionsReferences
23 ESD in Bulk and SOI FINFET
23.1 Early FinFET Structures23.2 FinFET Structure and Design Parameters 23.3 FinFET Parameters 23.4 Summary and Closing CommentsReferences
24 MEMs
24.1 Micro-electromechanical (MEM) Devices24.2 ESD Concerns in Micro-electromechanical (MEM) Devices 24.3 Actuators24.4 Micro-electromechanical (MEM) RF Switches24.5 Micro-electromechanical (MEM) Mirrors24.6 Summary and Closing CommentsReferences
25 Magnetic Recording
25.1 Magnetic Recording Technology25.2 Summary and Closing CommentsReferences
26 Photomasks
26.1 Photomasks and Reticles26.2 ESD Concerns in Photomasks26.3 Avalanche Breakdown in Photomasks26.4 Electrical Model in Photomasks26.5 Failure Defects in Photomasks 26.6 Summary and Closing CommentsReferences
A Glossary of Terms – EMC Terminology
B Appendix B. ESD Standards
B.1 ESD AssociationB.2 International Organization of StandardsB.3 Department of DefenseB.4 Military StandardsB.5 Airborne Standards and Lightning
C Index
D Wiley Series in Electrostatic Discharge (ESD) and Electrical Overstress (EOS)
D.1 Additional Wiley Texts
E ESD Design Rules
E.1 ESD Design Rule Check (DRC)E.2 Electrostatic Discharge (ESD) Layout Versus Schematic (LVS) VerificationE.3 ESD Electrical Rule Check (ERC)
F Guard Ring Design Rules
F.1 Latchup Design Rule Checking (DRC) and Guard RingsF.2 Latchup Electrical Rule Check (ERC)F.3 Guard Ring Resistance
G EOS Design Rules and Checklist
G.1 Electrical Overstress (EOS) Design Rule CheckingG.2 Electrical Overstress (EOS) Layout Versus Schematic (LVS) VerificationG.3 Electrical Overstress (EOS) Electrical Rule Check (ERC)
H Latchup Design Rules
H.1 Latchup Design Rule Checking (DRC)H.2 Latchup Electrical Rule Check (ERC)
I ESD Cookbook
Electrostatic Discharge (ESD) Cookbook
J EOS Cookbook
Electrical Overstress (EOS) Cookbook
K Latchup Cookbook
K.1 Latchup Design Rule Checking (DRC)K.2 Latchup Electrical Rule Check (ERC)
L ESD Design and Release Check List
L.1 ESD Design ReleaseL.2 Electrostatic Discharge (ESD) Checklists
M EOS Design and Release Checklist
M.1 Electrical Overstress (EOS) and ESD Design ReleaseM.2 Electrical Overstress (EOS) Design Release ProcessM.3 Electrical Overstress (EOS) ChecklistsM.4 An EOS Checklist
N Latchup Design and Release Checklist
N.1 Latchup Design Rule Checking (DRC)N.2 Latchup Electrical Rule Checking (ERC)N.3 Latchup ChecklistsN.4 A Latchup Design and Release Checklist
Index
End User License Agreement

Overview

A practical and comprehensive reference that explores Electrostatic Discharge (ESD) in semiconductor components and electronic systems

The ESD Handbook offers a comprehensive reference that explores topics relevant to ESD design in semiconductor components and explores ESD in various systems. Electrostatic discharge is a common problem in the semiconductor environment and this reference fills a gap in the literature by discussing ESD protection. Written by a noted expert on the topic, the text offers a topic-by-topic reference that includes illustrative figures, discussions, and drawings.

The handbook covers a wide-range of topics including ESD in manufacturing (garments, wrist straps, and shoes); ESD Testing; ESD device physics; ESD semiconductor process effects; ESD failure mechanisms; ESD circuits in different technologies (CMOS, Bipolar, etc.); ESD circuit types (Pin, Power, Pin-to-Pin, etc.); and much more. In addition, the text includes a glossary, index, tables, illustrations, and a variety of case studies.

Contains a well-organized reference that provides a quick review on a range of ESD topics
Fills the gap in the current literature by providing information from purely scientific and physical aspects to practical applications
Offers information in clear and accessible terms
Written by the accomplished author of the popular ESD book series

Written for technicians, operators, engineers, circuit designers, and failure analysis engineers, The ESD Handbook contains an accessible reference to ESD design and ESD systems.

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