The ESD Handbook

The ESD Handbook

by Steven H. Voldman
Released April 2021
Publisher(s): Wiley
ISBN: 9781119965176

Read it now on the O’Reilly learning platform with a 10-day free trial.

O’Reilly members get unlimited access to books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.

Start your free trial

Book description

A practical and comprehensive reference that explores Electrostatic Discharge (ESD) in semiconductor components and electronic systems 

The ESD Handbook offers a comprehensive reference that explores topics relevant to ESD design in semiconductor components and explores ESD in various systems. Electrostatic discharge is a common problem in the semiconductor environment and this reference fills a gap in the literature by discussing ESD protection. Written by a noted expert on the topic, the text offers a topic-by-topic reference that includes illustrative figures, discussions, and drawings.

The handbook covers a wide-range of topics including ESD in manufacturing (garments, wrist straps, and shoes); ESD Testing; ESD device physics; ESD semiconductor process effects; ESD failure mechanisms; ESD circuits in different technologies (CMOS, Bipolar, etc.); ESD circuit types (Pin, Power, Pin-to-Pin, etc.); and much more. In addition, the text includes a glossary, index, tables, illustrations, and a variety of case studies.

  • Contains a well-organized reference that provides a quick review on a range of ESD topics
  • Fills the gap in the current literature by providing information from purely scientific and physical aspects to practical applications
  • Offers information in clear and accessible terms
  • Written by the accomplished author of the popular ESD book series

Written for technicians, operators, engineers, circuit designers, and failure analysis engineers, The ESD Handbook contains an accessible reference to ESD design and ESD systems. 

Table of contents

  1. Cover
  2. Title Page
  3. Copyright
  4. Dedication
  5. About the Author
  6. Acknowledgements
  7. 1 ESD, EOS, EMI, EMC, and Latchup
    1. 1.1 Electrostatic Discharge (ESD)
    2. 1.2 Human Body Model (HBM)
    3. 1.3 Machine Model (MM)
    4. 1.4 Cassette Model
    5. 1.5 Charged Device Model (CDM)
    6. 1.6 Transmission Line Pulse (TLP)
    7. 1.7 Very Fast Transmission Line Pulse (VF-TLP)
    8. 1.8 Electrical Overstress (EOS)
    9. 1.9 Electrical Overstress (EOS)
    10. 1.10 EOS Sources – Lightning
    11. 1.11 EOS Sources – Electromagnetic Pulse (EMP)
    12. 1.12 EOS Sources – Machinery
    13. 1.13 EOS Sources – Power Distribution
    14. 1.14 EOS Sources – Switches, Relays, and Coils
    15. 1.15 EOS Design Flow and Product Definition
    16. 1.16 EOS Sources – Design Issues
    17. 1.17 Electromagnetic Interference (EMI)
    18. 1.18 Electromagnetic Compatibility (EMC)
    19. 1.19 Latchup
    20. Questions and Answers
    21. 1.20 Summary and Closing Comments
    22. References
  8. 2 ESD in Manufacturing
    1. 2.1 Flooring
    2. 2.2 Work Surfaces
    3. 2.3 Garments
    4. 2.4 Wrist Straps
    5. 2.5 Shoes – Footwear
    6. 2.6 Ionization
    7. 2.7 Clean Rooms
    8. 2.8 Carts
    9. 2.9 Shipping Tubes
    10. 2.10 Trays
    11. 2.11 Measurements
    12. 2.12 Verification
    13. 2.13 Audit
    14. 2.14 Triboelectric Charging – How Does it Happen?
    15. 2.15 Conductors, Semiconductors, and Insulators
    16. 2.16 Static Dissipative Materials
    17. 2.17 ESD and Materials
    18. 2.18 Electrification and Coulomb’s Law
    19. 2.19 Electromagnetism and Electrodynamics
    20. 2.20 Electrical Breakdown
    21. 2.21 Electro-Quasistatics and Magnetoquasistatics
    22. 2.22 Electrodynamics and Maxwell’s Equations
    23. 2.23 Electrostatic Discharge (ESD)
    24. 2.24 Electromagnetic Compatibility (EMC)
    25. 2.25 Electromagnetic Interference (EMI)
    26. 2.26 Fundamentals of Manufacturing and Electrostatics
    27. 2.27 Materials, Tooling, Human Factors, and Electrostatic Discharge
    28. 2.28 Materials and Human-induced Electric Fields
    29. 2.29 Manufacturing Environment and Tooling
    30. 2.30 Manufacturing Equipment and ESD Manufacturing Problems
    31. 2.31 Manufacturing Materials
    32. 2.32 Measurement and Test Equipment
    33. 2.33 Manufacturing Testing for Compliance
    34. 2.34 Grounding and Bonding Systems
    35. 2.35 Work Surfaces
    36. 2.36 Wrist Straps
    37. 2.37 Constant Monitors
    38. 2.38 Footwear
    39. 2.39 Floors
    40. 2.40 Personnel Grounding with Garments
    41. 2.41 Garments
    42. 2.42 Air Ionization
    43. 2.43 Seating
    44. 2.44 Packaging and Shipping
    45. 2.45 Trays
    46. 2.46 ESD Identification
    47. 2.47 ESD Program Auditing
    48. 2.48 ESD On-Chip Protection
    49. 2.49 ESD, EOS, EMI, EMC, and Latchup
    50. 2.50 Manufacturing Electrical Overstress (EOS)
    51. 2.51 EMI
    52. 2.52 EMC
    53. 2.53 Summary and Closing Comments
    54. References
  9. 3 ESD Standards
    1. 3.1 Factory – Flooring
    2. 3.2 Factory – Resistance Measurement of Materials
    3. 3.3 JEDEC
    4. 3.4 International Electro-Technical Commission (IEC)
    5. 3.5 IEEE
    6. 3.6 Department of Defense (DOD)
    7. 3.7 Military Standards
    8. 3.8 SAE
    9. 3.9 Summary and Closing Comments
    10. Questions and Answers
    11. References
  10. 4 ESD Testing
    1. 4.1 Electrostatic Discharge (ESD) Testing
    2. 4.2 ESD Models
    3. 4.3 HBM Test System
    4. 4.4 HBM Two-pin Test System
    5. 4.5 Machine Model (MM)
    6. 4.6 Small Charge Model (SCM)
    7. 4.7 Small Charge Model Source
    8. 4.8 CDM Pulse Waveform
    9. 4.9 HMM Equivalent Circuit
    10. 4.10 HMM Test Equipment
    11. 4.11 HMM Test Configuration
    12. 4.12 HMM Fixture Board
    13. 4.13 Transmission Line Pulse (TLP)
    14. 4.14 TLP Test Systems
    15. 4.15 IEC 61000-4-2
    16. 4.16 Equivalent Circuit
    17. 4.17 Test Equipment
    18. 4.18 Cable Discharge Event (CDE)
    19. 4.19 CDE Pulse Waveform
    20. 4.20 Equivalent Circuit
    21. 4.21 Commercial Test Systems
    22. 4.22 Systems Electromagnetic Interference (EMI)
    23. 4.23 Electromagnetic Compatibility (EMC)
    24. 4.24 Electrical Overstress (EOS)
    25. 4.25 Latchup
    26. 4.26 Electrical Overstress (EOS)
    27. 4.27 EOS Sources – Lightning
    28. 4.28 EOS Sources – Electromagnetic Pulse (EMP)
    29. 4.29 Electromagnetic Compatibility
    30. 4.30 Summary and Closing Comments
    31. References
  11. 5 ESD Device Physics
    1. 5.1 Electro-thermal Instability
    2. 5.2 Stable System
    3. 5.3 Unstable System
    4. 5.4 Differential Relation of Voltage and Current
    5. 5.5 Time Constant Hierarchy
    6. 5.6 Thermal Physics Time Constants
    7. 5.7 Adiabatic, Thermal Diffusion Time Scale and Steady State
    8. 5.8 Electro-quasistatic and Magnetoquasistatics
    9. 5.9 Electrical Instability
    10. 5.10 Thermal Physics Time Constants
    11. 5.11 Adiabatic, Thermal Diffusion Time Scale and Steady State
    12. 5.12 Electrical Instability and Breakdown
    13. 5.13 Spatial Instability and Electro-thermal Current Constriction
    14. 5.14 Equipotential Surface
    15. 5.15 Heat Flow
    16. 5.16 Conservation of Heat
    17. 5.17 Electric Potential and Temperature Gradient
    18. 5.18 Electric Energy, Resistivity, and Thermal Conductivity
    19. 5.19 Breakdown
    20. 5.20 Electron Current Continuity Relationship
    21. 5.21 Air Breakdown and Peak Currents
    22. 5.22 Electro-thermal Instability
    23. 5.23 Mathematical Methods – Green’s Function and Method of Images
    24. 5.24 Mathematical Methods – Green’s Function and Method of Images
    25. 5.25 Mathematical Methods – Integral Transforms of the Heat Conduction Equation
    26. 5.26 Flux Potential Transfer Relations Matrix Methodology
    27. 5.27 Heat Equation Variable Conductivity
    28. 5.28 Mathematical Methods – Boltzmann Transformation
    29. 5.29 Mathematical Methods – The Duhamel Formulation
    30. 5.30 Spherical Source Tasca Model
    31. 5.31 Wunsch–Bell Model
    32. 5.32 The Smith and Littau Model
    33. 5.33 The Arkihpov–Astvatsaturyan–Godovosyn–Rudenko Model
    34. 5.34 The Vlasov–Sinkevitch Model
    35. 5.35 The Dwyer, Franklin and Campbell Model
    36. 5.36 Negative Differential Resistor and Resistor Ballasting
    37. 5.37 Ash Model – Nonlinear Failure Power Thresholds
    38. 5.38 Statistical Models for ESD Prediction
    39. 5.39 Summary and Closing Comments
    40. References
  12. 6 ESD Events and Protection Circuits
    1. 6.1 Human Body Model (HBM)
    2. 6.2 Machine Model (MM)
    3. 6.3 Charged Device Model
    4. 6.4 Human Metal Model (HMM)
    5. 6.5 IEC 61000-4-2 History
    6. 6.6 IEC 61000-4-5
    7. 6.7 Cable Discharge Event (CDE)
    8. 6.8 CDM Scope
    9. References
  13. 7 ESD Failure Mechanism
    1. 7.1 Tables of CMOS ESD Failure Mechanisms
    2. 7.2 LOCOS Isolation-Defined CMOS
    3. 7.3 LOCOS-bound Thick Oxide MOSFET
    4. 7.4 LOCOS-Bound Structures
    5. 7.5 Shallow Trench Isolation (STI)
    6. 7.6 STI Pull-down ESD Failure Mechanism
    7. 7.7 STI Pull-Down and Gate Wrap-Around
    8. 7.8 MOSFETs
    9. 7.9 LOCOS-bound Thick Oxide MOSFET
    10. 7.10 Bipolar Transistor Devices
    11. 7.11 Silicide Blocked N-diffusion Resistors
    12. 7.12 Silicon Germanium ESD Failure Mechanisms
    13. 7.13 Silicon Germanium Carbon ESD Failure Mechanisms
    14. 7.14 Gallium Arsenide Technology ESD Failure Mechanisms
    15. 7.15 Indium Gallium Arsenide ESD Failure Mechanisms
    16. 7.16 Micro Electromechanical (MEM) Systems
    17. 7.17 Micro-mirror Array Failures
    18. 7.18 EOS Bond Pad and Interconnect Failure
    19. 7.19 Summary and Closing Comments
    20. References
  14. 8 ESD Design Synthesis
    1. 8.1 ESD Design Synthesis and Architecture Flow
    2. 8.2 ESD Design – the Signal Path and the Alternate Current Path
    3. 8.3 ESD Electrical Circuit and Schematic Architecture Concepts
    4. 8.4 The Ideal ESD Network
    5. 8.5 Mapping Semiconductor Chips and ESD Designs
    6. 8.6 Mapping across Semiconductor Fabricators
    7. 8.7 ESD Design Mapping across Technology Generations
    8. 8.8 ESD Networks, Sequencing, and Chip Architecture
    9. 8.9 ESD Layout and Floorplan-related Concepts
    10. 8.10 ESD Architecture and Floor-planning
    11. 8.11 Digital and Analog CMOS Architecture
    12. 8.12 Digital and Analog Floorplan – Placement of Analog Circuits
    13. 8.13 Mixed-signal Architecture – Digital, Analog, and RF Architecture
    14. 8.14 Summary and Closing Comments
    15. Questions
    16. References
  15. 9 On-chip ESD Protection Circuits – Input Circuitry
    1. 9.1 Receivers and ESD
    2. 9.2 Receivers and Receiver Delay Time
    3. 9.3 ESD Loading Effect on Receiver Performance
    4. 9.4 Receivers and HBM
    5. 9.5 Receivers and CDM
    6. 9.6 Receivers and Receiver Evolution
    7. 9.7 Receiver Circuits with Half-pass Transmission Gate
    8. 9.8 Receiver with Full-pass Transmission Gate
    9. 9.9 Receiver, Half-pass Transmission Gate, and Keeper Network
    10. 9.10 Receiver, Half-pass Transmission Gate, and the Modified Keeper Network
    11. 9.11 Receiver Circuits with Pseudo-zero VT Half-pass Transmission Gates
    12. 9.12 Receiver with Zero VT Transmission Gate
    13. 9.13 Receiver Circuits with Bleed Transistors
    14. 9.14 Receiver Circuits with Test Functions
    15. 9.15 Receiver with Schmitt Trigger Feedback Network
    16. 9.16 Bipolar Transistor Receivers
    17. 9.17 CMOS Differential Receiver with Analog Layout Concepts
    18. 9.18 CMOS Differential Receiver Capacitance Loading
    19. 9.19 CMOS Differential Receiver ESD Mismatch
    20. 9.20 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout
    21. 9.21 Analog Differential Pair Common Centroid Design Layout – Signal-Pin to Signal-Pin and Parasitic ESD Elements
    22. 9.22 Off-chip Drivers (OCD)
    23. 9.23 Off-chip Driver I/O Standards and ESD
    24. 9.24 Off-chip Driver (OCD) ESD Design Basics
    25. 9.25 Off-chip Drivers (OCD): Mixed Voltage Interface
    26. 9.26 Off-chip Drivers (OCD): Self-bias Well OCD Networks
    27. 9.27 Self-bias Well Off-chip Driver (OCD) Networks
    28. 9.28 ESD Protection Networks for Self-bias Well OCD Networks
    29. 9.29 Programmable Impedance Off-chip Driver (OCD) Network
    30. 9.30 ESD Input Protection Networks for Programmable Impedance Off-chip Drivers
    31. 9.31 Universal Off-chip Drivers
    32. 9.32 Gate Array Off-chip Driver Design
    33. 9.33 Gate Array OCD Design – Impedance Matching of Unused Elements
    34. 9.34 OCD ESD Design – Power Rails Over Multi-finger MOSFETs
    35. 9.35 Off-chip Driver: Gate-modulated MOSFET ESD Network
    36. 9.36 Off-chip Driver Simplified Gate Modulated Network
    37. 9.37 Off-chip Drivers ESD Design: Integration of Coupling and Ballasting Techniques
    38. 9.38 Ballasting and Coupling
    39. 9.39 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with Diode
    40. 9.40 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with a MOSFET
    41. 9.41 Gate-coupled Domino Resistor-ballasted MOSFET
    42. 9.42 Substrate-modulated Resistor Ballasted MOSFET
    43. 9.43 Summary and Closing Comments
    44. Problems
    45. References
  16. 10 On-Chip ESD Protection Circuits – ESD Power Clamps
    1. 10.1 ESD Power Clamps
    2. 10.2 ESD Power Clamp Design Practices
    3. 10.3 Current Loops
    4. 10.4 Impedance
    5. 10.5 Segmentation
    6. 10.6 Voltage Limitations
    7. 10.7 Latchup
    8. 10.8 ESD Power Clamp Circuits
    9. 10.9 Classification of ESD Power Clamps
    10. 10.10 Master-Slave ESD Power Clamps
    11. 10.11 Trigger Networks
    12. 10.12 ESD Power Clamp Characteristics and Issues
    13. 10.13 Design Synthesis of ESD Power Clamp – Key Design Parameters
    14. 10.14 Design Synthesis of ESD Power Clamps Trigger Networks
    15. 10.15 Transient Response Frequency Trigger Element and the ESD Frequency Window
    16. 10.16 ESD Power Clamp Frequency Design Window
    17. 10.17 Design Synthesis of ESD Power Clamp – Voltage Triggered ESD Trigger Elements
    18. 10.18 Design Synthesis of ESD Power Clamp – The ESD Power Clamp Shunting Element
    19. 10.19 ESD Power Clamp Trigger Condition vs. Shunt Failure
    20. 10.20 ESD Clamp Element – Width Scaling
    21. 10.21 ESD Clamp Element – On-resistance
    22. 10.22 ESD Clamp Element – Safe Operating Area (SOA)
    23. 10.23 ESD Power Clamp Issues
    24. 10.24 ESD Power Clamp Issues – Power-up and Power-down
    25. 10.25 ESD Power Clamp Issues – False Triggering
    26. 10.26 ESD Power Clamp Issues – Pre-charging
    27. 10.27 ESD Power Clamp Issues – Post-charging
    28. 10.28 ESD Power Clamp Design
    29. 10.29 ESD Power Clamp Design Synthesis – Forward Bias Triggered ESD Power Clamps
    30. 10.30 Series Stacked RC-triggered ESD Power Clamps
    31. 10.31 Triple Well Diode String ESD Power Clamp
    32. 10.32 Bipolar ESD Power Clamps
    33. 10.33 ESD Power Clamp Design Synthesis – Bipolar ESD Power Clamps
    34. 10.34 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance-triggered
    35. 10.35 Silicon Controlled Rectifier Power Clamps
    36. Problems
    37. References
  17. 11 ESD Architecture and Floor Planning
    1. 11.1 ESD Design Floor Plan
    2. 11.2 Peripheral I/O Design
    3. 11.3 Pad Limited Peripheral I/O Design Architecture
    4. 11.4 Pad Limited Peripheral I/O Design Architecture – Staggered I/O
    5. 11.5 Core Limited Peripheral I/O Design Architecture
    6. 11.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture
    7. 11.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners
    8. 11.8 Lumped ESD Power Clamp in Peripheral I/O Design Architecture – Power Pads
    9. 11.9 Lumped ESD Power Clamp in Peripheral I/O Design Architecture – Master/Slave ESD Power Clamp System
    10. 11.10 Array I/O
    11. 11.11 Array I/O Nibble Architecture
    12. 11.12 Array I/O Pair Architecture
    13. 11.13 Array I/O – Fully Distributed
    14. 11.14 ESD Architecture – Dummy Bus Architecture
    15. 11.15 ESD Architecture – Dummy VDD Bus
    16. 11.16 ESD Architecture – Dummy Ground (VSS) Bus
    17. 11.17 Native Voltage Power Supply Architecture
    18. 11.18 Single Power Supply Architecture
    19. 11.19 Mixed Voltage Architecture
    20. 11.20 Mixed Voltage Architecture – Single Power Supply
    21. 11.21 Mixed Voltage Architecture – Dual Power Supply
    22. 11.22 Mixed Signal Architecture
    23. 11.23 Digital and Analog Floor Plan – Placement of Analog Circuits
    24. 11.24 Mixed Signal Architecture – Digital, Analog, and RF Architecture
    25. 11.25 ESD Power Grid Design
    26. 11.26 I/O to Core Guard Rings
    27. 11.27 Within I/O Guard Rings
    28. 11.28 ESD-to-I/O Off-Chip Driver (OCD) Guard Ring
    29. 11.29 Guard Rings and Computer Aided Design (CAD) Methods
    30. 11.30 Summary and Closing Comments
    31. References
  18. 12 ESD Digital Design
    1. 12.1 Fundamental Concepts of ESD Design
    2. 12.2 Concepts of ESD Digital Design
    3. 12.3 Device Response to External Events
    4. 12.4 Alternative Current Loops
    5. 12.5 Decoupling of Feedback Loops
    6. 12.6 Decoupling of Power Rails
    7. 12.7 Local and Global Distribution
    8. 12.8 Usage of Parasitic Elements
    9. 12.9 Unused Section of a Semiconductor Device, Circuit, or Chip Function
    10. 12.10 Unused Corners
    11. 12.11 Unused White Space
    12. 12.12 Impedance Matching Between Floating and Non-floating Networks
    13. 12.13 Unconnected Structures
    14. 12.14 Symmetry
    15. 12.15 Design Synthesis
    16. 12.16 ESD, Latchup, and Noise
    17. 12.17 Structures Under Bond Pads
    18. 12.18 Summary and Closing Comments
    19. References
  19. 13 ESD Analog Design
    1. 13.1 Analog Design: Local Matching
    2. 13.2 Analog Design: Global Matching
    3. 13.3 Symmetry
    4. 13.4 Analog Design – Local Matching
    5. 13.5 Analog Design – Global Matching
    6. 13.6 Common Centroid Design
    7. 13.7 Common Centroid Arrays
    8. 13.8 Interdigitation Design
    9. 13.9 Common Centroid and Interdigitation Design
    10. 13.10 Dummy Resistor Layout
    11. 13.11 Thermoelectric Cancelation Layout
    12. 13.12 Electrostatic Shield
    13. 13.13 Interdigitated Resistors and ESD Parasitics
    14. 13.14 Capacitor Element Design
    15. 13.15 Inductor Element Design
    16. 13.16 ESD Failure in Inductors
    17. 13.17 Inductor Physical Variables
    18. 13.18 Inductor Element Design
    19. 13.19 Diode Design
    20. 13.20 Analog ESD Circuits
    21. 13.21 ESD MOSFETs
    22. 13.22 Receivers
    23. 13.23 CMOS Differential Receiver with Analog Layout Concepts
    24. 13.24 Analog Differential Pair Common Centroid Design Layout – Signal-pin to Signal-pin and Parasitic ESD Elements
    25. 13.25 Summary and Closing Comments
    26. References
  20. 14 ESD RF Design
    1. 14.1 Fundamental Concepts of ESD Design
    2. 14.2 Fundamental Concepts of RF ESD Design
    3. 14.3 RF CMOS Input Circuits
    4. 14.4 RF CMOS Impedance Isolation LC Resonator ESD Networks
    5. 14.5 RF CMOS LC-diode Networks Experimental Results
    6. 14.6 RF CMOS LNA ESD Design – Low Resistance ESD Inductor and ESD Diode Clamping Elements in Π-configuration
    7. 14.7 RF CMOS T-coil Inductor ESD Input Network
    8. 14.8 RF CMOS Distributed ESD Networks
    9. 14.9 RF CMOS Distributed ESD-RF Networks
    10. 14.10 RF CMOS Distributed RF-ESD Networks Using Series Inductors and Dual-diode Shunts
    11. 14.11 RF CMOS Distributed RF-ESD Networks Using Series Inductors and MOSFET Parallel Shunts
    12. 14.12 RF CMOS Distributed ESD Networks – Transmission Lines and Co-planar Waveguides
    13. 14.13 RF CMOS – ESD and RF LDMOS Power Technology
    14. 14.14 Summary and Closing Comments
    15. References
  21. 15 ESD Power Electronics Design
    1. 15.1 Reliability Technology Scaling and the Reliability Bathtub Curve
    2. 15.2 Input Circuitry
    3. 15.3 Summary and Closing Comments
    4. References
  22. 16 ESD in Advanced CMOS
    1. 16.1 Interconnects and ESD
    2. 16.2 Aluminum Interconnects
    3. 16.3 Interconnects – Vias
    4. 16.4 Interconnects – Wiring
    5. 16.5 Junctions
    6. 16.6 Titanium Silicide
    7. 16.7 Shallow Trench Isolation
    8. 16.8 LOCOS-bound ESD Structures
    9. 16.9 LOCOS-bound p+/n-well Junction Diodes
    10. 16.10 LOCOS-bound n+ Junction Diodes
    11. 16.11 LOCOS-bound n-well/Substrate Diodes
    12. 16.12 LOCOS-bound Lateral N-Well to N-Well Bipolar ESD Element
    13. 16.13 LOCOS-bound Lateral N+ to N-well Bipolar ESD Element
    14. 16.14 LOCOS-bound Lateral pnp Bipolar ESD Element
    15. 16.15 LOCOS-bound Thick Oxide MOSFET ESD Element
    16. 16.16 Shallow Trench Isolation
    17. 16.17 STI-bound ESD Structures
    18. 16.18 Substrate Modeling – Electrical and Thermal Discretization
    19. 16.19 Heavily Doped Substrates
    20. 16.20 Retrograde Wells and ESD Scaling
    21. 16.21 Triple Well and Isolated MOSFET CMOS
    22. 16.22 Summary and Closing Comments
    23. References
  23. 17 ESD in Silicon on Insulator
    1. 17.1 Silicon on Insulator (SOI) Technologies
    2. 17.2 Elimination of CMOS Latchup
    3. 17.3 Lack of Vertical Bipolar Transistors
    4. 17.4 Floating Gate Tie Downs
    5. 17.5 Physical Separation of MOSFETs from the Bulk Substrate
    6. 17.6 SOI ESD Design Fundamental Concepts
    7. 17.7 SOI Lateral Diode Structure
    8. 17.8 Transistors – Bulk versus SOI Technology
    9. 17.9 SOI Buried Resistors (BR) Elements
    10. 17.10 Dynamic Threshold MOS (DTMOS) SOI MOSFET
    11. 17.11 SOI P+ Body Contact Abutting n+ Drain
    12. 17.12 Transmission Line Pulse (TLP) Testing of SOI Diode Designs
    13. 17.13 SOI ESD with MOSFET Drain and Body Width Ratio Variation
    14. 17.14 SOI Dual-Gate MOSFET Structure
    15. 17.15 SOI ESD Design – Mixed Voltage T-Shape Layout Style
    16. 17.16 SOI ESD Design: Double Diode Network
    17. 17.17 Bulk to SOI ESD Design Remapping
    18. 17.18 SOI ESD Diode Design Parameters
    19. 17.19 SOI ESD Design in Mixed Voltage Interface Environments
    20. 17.20 Comparison of Bulk with SOI ESD Results
    21. 17.21 SOI ESD Design with Aluminum Interconnects
    22. 17.22 SOI ESD Design with Copper Interconnects
    23. 17.23 SOI ESD Design with Gate Circuitry
    24. 17.24 Summary and Closing Comments
    25. References
  24. 18 ESD in Analog Circuits
    1. 18.1 Analog Design Circuits
    2. 18.2 Single-ended Receivers
    3. 18.3 Schmitt Trigger Receivers
    4. 18.4 Differential Receivers
    5. 18.5 Comparators
    6. 18.6 Current Sources
    7. 18.7 Current Mirrors
    8. 18.8 Widlar Current Mirror
    9. 18.9 Wilson Current Mirror
    10. 18.10 Voltage Regulators
    11. 18.11 Buck Converters
    12. 18.12 Boost Converters
    13. 18.13 Buck-Boost Converters
    14. 18.14 Cuk Converters
    15. 18.15 Voltage Reference Circuits
    16. 18.16 Brokaw Bandgap Voltage Reference
    17. 18.17 Converters
    18. 18.18 Analog-to-Digital Converter (ADC)
    19. 18.19 Digital-to-Analog Converters (DAC)
    20. 18.20 Oscillators
    21. 18.21 Phase Lock Loop (PLL) Circuits
    22. 18.22 Delay Locked Loop (DLL)
    23. 18.23 Analog and ESD Design Synthesis
    24. 18.24 Analog Chip Architecture – Separation of Analog Power from Digital Power, AVDD–DVDD
    25. 18.25 ESD Failure in Phase Lock Loop (PLL) and System Clock
    26. 18.26 ESD Failure in Current Mirrors
    27. 18.27 ESD Failure in Schmitt Trigger Receivers
    28. 18.28 ESD Design Practice – Prevent ESD Failure in Schmitt Trigger
    29. 18.29 Analog–Digital Architecture: Isolated Digital and Analog Domains
    30. 18.30 ESD Protection Solution – Connectivity of AVDD-to-VDD
    31. 18.31 ESD Solution: Connectivity of AVSS-to-DVSS
    32. 18.32 Digital and Analog Domain with ESD Power Clamps
    33. 18.33 Digital and Analog Domain with Master–Slave ESD Power Clamps
    34. 18.34 High Voltage, Digital, and Analog Domain Floorplan
    35. 18.35 Floor-planning of Digital and Analog
    36. 18.36 Inter-domain Signal Lines ESD Failures
    37. 18.37 Digital-to-Analog Signal Line ESD Failures
    38. 18.38 Digital-to-Analog Core Spatial Isolation
    39. 18.39 Digital-to-Analog Core Ground Coupling
    40. 18.40 Digital-to-Analog Core Resistive Ground Coupling
    41. 18.41 Digital-to-Analog Core Diode Ground Coupling
    42. 18.42 Domain-to-Domain Signal Line ESD Networks
    43. 18.43 Domain-to-Domain Third-party Coupling Networks
    44. 18.44 Domain-to-Domain Cross-domain ESD Power Clamp
    45. 18.45 Digital-to-Analog Domain Moat
    46. 18.46 Analog and ESD Circuit Integration
    47. 18.47 Integrated Body Ties
    48. 18.48 Self-Protecting vs Non-self Protecting Designs
    49. References
  25. 19 ESD in RF CMOS
    1. 19.1 CMOS and ESD
    2. 19.2 RF CMOS
    3. 19.3 RF CMOS and ESD
    4. 19.4 RF CMOS ESD Failure Mechanisms
    5. 19.5 RF CMOS – ESD Device Comparisons
    6. 19.6 RF ESD Metrics
    7. 19.7 Grounded Gate n-channel MOSFET versus STI Diode
    8. 19.8 Silicon-controlled Rectifier
    9. 19.9 SCR versus GGNMOS
    10. 19.10 Shallow Trench Isolation and Polysilicon Gated Diodes
    11. 19.11 RF ESD Design
    12. 19.12 RF ESD Design Layout – Circular RF ESD Devices
    13. 19.13 Disadvantage of RF ESD Circular Element
    14. 19.14 RF ESD Design – ESD Wiring Design
    15. 19.15 RF ESD Design – Loading Capacitance
    16. 19.16 Metal Capacitance
    17. 19.17 Analog Metal (AM)
    18. 19.18 RF ESD Design Practices
    19. 19.19 RF Passives – ESD and Schottky Barrier Diodes
    20. 19.20 Schottky Barrier Diodes and Metallurgy
    21. 19.21 Silicon Germanium Schottky Barrier Diodes
    22. 19.22 Schottky Barrier RF ESD Design Practice
    23. 19.23 RF Passives – ESD and Inductors
    24. 19.24 Quality Factor, Q
    25. 19.25 Incremental Model of an Inductor
    26. 19.26 Inductor Coil Parameters
    27. 19.27 RF Passives – ESD and Capacitors
    28. 19.28 Capacitors and RF Applications
    29. 19.29 Capacitors in ESD Networks
    30. 19.30 Types of Radio Frequency Capacitors
    31. 19.31 Metal-Oxide-Semiconductor and Metal-Insulator-Metal Capacitors
    32. 19.32 Varactors and Hyper-abrupt Junction Varactor Capacitors
    33. 19.33 Metal-ILD-Metal Capacitors
    34. 19.34 Vertical Parallel Plate (VPP) Capacitors
    35. 19.35 Tips: ESD RF Design Practices for Capacitors
    36. 19.36 Summary and Closing Comments
    37. Problems
    38. References
  26. 20 ESD in Silicon Germanium
    1. 20.1 Heterojunctions Bipolar Transistors
    2. 20.2 Silicon Germanium
    3. 20.3 Silicon Germanium HBT Devices
    4. 20.4 Silicon Germanium Device Structure
    5. 20.5 Silicon Germanium Film Deposition
    6. 20.6 Silicon Germanium Emitter–Base Region
    7. 20.7 Silicon Germanium Physics
    8. 20.8 Silicon Germanium Bandgap
    9. 20.9 Silicon Germanium Intrinsic Temperature
    10. 20.10 Position-dependent Silicon Germanium Profile
    11. 20.11 Position-dependent Intrinsic Temperature
    12. 20.12 SiGe Collector Current with Graded Germanium Concentration
    13. 20.13 Silicon Germanium ESD and Time Constants
    14. 20.14 Silicon Germanium Base Transit Time
    15. 20.15 Silicon Germanium Breakdown Voltages
    16. 20.16 Silicon Germanium ESD Measurements
    17. 20.17 Silicon Germanium Collector-to-Emitter ESD Stress
    18. 20.18 Transmission Line Pulse Testing of Silicon Germanium HBT
    19. 20.19 Transmission Line Pulse (TLP) I-V Characteristic
    20. 20.20 Wunsch–Bell Characteristic of Silicon Germanium HBT
    21. 20.21 Comparison of Silicon Germanium HBT and Silicon BJT
    22. 20.22 Wunsch–Bell Characteristic of SiGe HBT versus Si BJT
    23. 20.23 Intrinsic Base Resistance in SiGe HBT
    24. 20.24 SiGe HBT Electro-thermal HBM Simulation of Collector–Emitter Stress
    25. 20.25 Silicon Germanium Transistor Emitter–Base Design
    26. 20.26 Epitaxial-Base Hetero-Junction Bipolar Transistor (HBT) Emitter–Base Design
    27. 20.27 Self-aligned Silicon Germanium HBT Device
    28. 20.28 Non-Self Aligned Silicon Germanium HBT
    29. 20.29 Emitter–Base Design RF Frequency Performance Metrics
    30. 20.30 SiGe HBT Emitter–Base Resistance Model
    31. 20.31 SiGe HBT Emitter–Base Design and Silicide Placement
    32. 20.32 Silicide Material and ESD
    33. 20.33 Titanium Silicide and ESD
    34. 20.34 Cobalt Salicide
    35. 20.35 Self-aligned (SA) Emitter Base Design
    36. 20.36 Non-Self Aligned (NSA) Emitter Base Design
    37. 20.37 Non-Self Aligned HBT Human Body Model (HBM) Step Stress
    38. 20.38 Transmission Line Pulse (TLP) Step Stress
    39. 20.39 RF Testing of SiGe HBT Emitter–Base Configuration
    40. 20.40 Unity Current Gain Cutoff Frequency – Collector Current Plots
    41. 20.41 fMAX and fT
    42. 20.42 Electrothermal Simulation of Emitter–Base Stress
    43. 20.43 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data
    44. 20.44 Silicon Germanium HBT Multiple-emitter Study
    45. 20.45 RF ESD Design Practice
    46. 20.46 Silicon Germanium ESD Failure Mechanisms
    47. 20.47 Summary and Closing Comments
    48. References
  27. 21 ESD in Silicon Germanium Carbon
    1. 21.1 Heterojunctions and Silicon Germanium Carbon Technology
    2. 21.2 Silicon Germanium Carbon
    3. 21.3 Silicon Germanium Carbon Collector–Emitter ESD Measurements
    4. 21.4 Silicon Germanium Transistor Emitter–Base Design
    5. 21.5 Silicon Germanium Carbon – ESD-Induced S-Parameter Degradation
    6. 21.6 Silicon Germanium Carbon ESD Failure Mechanisms
    7. 21.7 Summary and Closing Comments
    8. References
  28. 22 ESD in GaAs
    1. 22.1 Gallium Arsenide Technology and ESD
    2. 22.2 Gallium Arsenide Energy-to-Failure, and Power-to-Failure
    3. 22.3 Gallium Arsenide ESD Failures in Active and Passive Elements
    4. 22.4 Gallium Arsenide HBT Devices and ESD
    5. 22.5 Gallium Arsenide HBT Device ESD Results
    6. 22.6 Gallium Arsenide HBT Diode Strings
    7. 22.7 Gallium Arsenide HBT-based Passive Elements
    8. 22.8 GaAs HBT Base–Collector Varactor
    9. 22.9 Gallium Arsenide Technology Table of Failure Mechanisms
    10. 22.10 Application – GaAs Power Amplifier in a Cell Phone
    11. 22.11 Summary and Closing Comments
    12. Questions
    13. References
  29. 23 ESD in Bulk and SOI FINFET
    1. 23.1 Early FinFET Structures
    2. 23.2 FinFET Structure and Design Parameters
    3. 23.3 FinFET Parameters
    4. 23.4 Summary and Closing Comments
    5. References
  30. 24 MEMs
    1. 24.1 Micro-electromechanical (MEM) Devices
    2. 24.2 ESD Concerns in Micro-electromechanical (MEM) Devices
    3. 24.3 Actuators
    4. 24.4 Micro-electromechanical (MEM) RF Switches
    5. 24.5 Micro-electromechanical (MEM) Mirrors
    6. 24.6 Summary and Closing Comments
    7. References
  31. 25 Magnetic Recording
    1. 25.1 Magnetic Recording Technology
    2. 25.2 Summary and Closing Comments
    3. References
  32. 26 Photomasks
    1. 26.1 Photomasks and Reticles
    2. 26.2 ESD Concerns in Photomasks
    3. 26.3 Avalanche Breakdown in Photomasks
    4. 26.4 Electrical Model in Photomasks
    5. 26.5 Failure Defects in Photomasks
    6. 26.6 Summary and Closing Comments
    7. References
  33. A Glossary of Terms – EMC Terminology
  34. B Appendix B. ESD Standards
    1. B.1 ESD Association
    2. B.2 International Organization of Standards
    3. B.3 Department of Defense
    4. B.4 Military Standards
    5. B.5 Airborne Standards and Lightning
  35. C Index
  36. D Wiley Series in Electrostatic Discharge (ESD) and Electrical Overstress (EOS)
    1. D.1 Additional Wiley Texts
  37. E ESD Design Rules
    1. E.1 ESD Design Rule Check (DRC)
    2. E.2 Electrostatic Discharge (ESD) Layout Versus Schematic (LVS) Verification
    3. E.3 ESD Electrical Rule Check (ERC)
  38. F Guard Ring Design Rules
    1. F.1 Latchup Design Rule Checking (DRC) and Guard Rings
    2. F.2 Latchup Electrical Rule Check (ERC)
    3. F.3 Guard Ring Resistance
  39. G EOS Design Rules and Checklist
    1. G.1 Electrical Overstress (EOS) Design Rule Checking
    2. G.2 Electrical Overstress (EOS) Layout Versus Schematic (LVS) Verification
    3. G.3 Electrical Overstress (EOS) Electrical Rule Check (ERC)
  40. H Latchup Design Rules
    1. H.1 Latchup Design Rule Checking (DRC)
    2. H.2 Latchup Electrical Rule Check (ERC)
  41. I ESD Cookbook
    1. Electrostatic Discharge (ESD) Cookbook
  42. J EOS Cookbook
    1. Electrical Overstress (EOS) Cookbook
  43. K Latchup Cookbook
    1. K.1 Latchup Design Rule Checking (DRC)
    2. K.2 Latchup Electrical Rule Check (ERC)
  44. L ESD Design and Release Check List
    1. L.1 ESD Design Release
    2. L.2 Electrostatic Discharge (ESD) Checklists
  45. M EOS Design and Release Checklist
    1. M.1 Electrical Overstress (EOS) and ESD Design Release
    2. M.2 Electrical Overstress (EOS) Design Release Process
    3. M.3 Electrical Overstress (EOS) Checklists
    4. M.4 An EOS Checklist
  46. N Latchup Design and Release Checklist
    1. N.1 Latchup Design Rule Checking (DRC)
    2. N.2 Latchup Electrical Rule Checking (ERC)
    3. N.3 Latchup Checklists
    4. N.4 A Latchup Design and Release Checklist
  47. Index
  48. End User License Agreement

Product information

  • Title: The ESD Handbook
  • Author(s): Steven H. Voldman
  • Release date: April 2021
  • Publisher(s): Wiley
  • ISBN: 9781119965176