The ESD Handbook

7ESD Failure Mechanism

Electrostatic discharge (ESD) failure can occur in silicon devices as well as in magnetic recording devices [100–102]. Many failure analysis tools exist to quantify ESD failure [12, 35–74]. In this chapter, additional references are included of ESD failures [15, 21–34, 74–99].

7.1 Tables of CMOS ESD Failure Mechanisms

Table 7.1 contains the ESD failure mechanisms in complementary metal-oxide semiconductor (CMOS) Local oxidation (LOCOS) isolation technology for early CMOS technology generations from 2 to 0.25 µm ground rule minimum.

Table 7.2 contains the ESD failure mechanisms in CMOS shallow trench isolation (STI) technology for the CMOS technology generations from 0.5 µm to 32 nm technology.

Table 7.3 contains the ESD failure mechanisms by technology generation highlighting the new mechanism that occurred at that technology node. With CMOS evolution, there has been transitions in the isolation process, metallurgical junction metal oxide semiconductor field effect transistor (MOSFET) source and drain, silicide material, MOSFET gate structure, and interconnects. The table will contain from 0.5 µm to 22 nm technology failure mechanisms.

Table 7.4 contains the ESD failure mechanisms observed in multi-gate technologies, and FINFET devices. Table 7.5 shows additional failure mechanisms.

7.2 LOCOS Isolation-Defined CMOS

Isolation structures have a significant influence on the electrical and thermal properties of a semiconductor device under high current ...