The ESD Handbook

8ESD Design Synthesis

8.1 ESD Design Synthesis and Architecture Flow

In the electrostatic discharge (ESD) design synthesis process, there is a flow of steps and procedures to construct a semiconductor chip [1–13]. In many cases, the floor planning process is a function of the type of semiconductor chip. The following design synthesis procedure is an example of an ESD design flow needed for semiconductor chip implementations:

• I/O, Domains, and Core Floorplan: Define floor plan of regions of cores, domains, and peripheral I/O circuitry.
• I/O Floor plan: Define area and placement for I/O circuitry.
• ESD Signal Pin Floor plan: Define ESD area and placement.
• ESD Power Clamp Network Floorplan: Define ESD power clamp area and placement for a given domain.
• ESD Domain-to-Domain Network Floorplan: Define ESD networks between the different chip domains area and placement for a given domain.
• ESD Signal Pin Network Definition: Define ESD network for the I/O circuitry.
• ESD Power Clamp Network Definition: Define ESD power clamp network within a power domain.
• Power Bus Definition and Placement: Define placement, bus width, and resistance requirements for the power bus.
• Ground Bus Definition and Placement: Define placement, bus width and resistance requirements for the ground bus.
• I/O to ESD Guard Rings: Define guard rings between I/O and ESD networks.
• I/O Internal Guard Rings: Define guard rings within the I/O circuitry.
• I/O External Guard Rings: Define guard rings between I/O circuitry and ...