The ESD Handbook

10On-Chip ESD Protection Circuits – ESD Power Clamps

10.1 ESD Power Clamps

In this chapter, electrostatic discharge (ESD) power clamp networks will be explored. ESD power clamps usage began in the mid-1990s, and today is a common practice of semiconductor chip design and ESD design synthesis [1–57]. Development of ESD power clamps and the synthesis into the semiconductor chip architecture is part of the ESD design discipline and an essential component of the art of ESD design. The chapter will focus on the classification of the ESD power clamps, key design parameters, the ESD power clamp design window, trigger elements, clamp devices and issues and problems with ESD power clamps.

10.2 ESD Power Clamp Design Practices

An ESD design practice is the integration of ESD power clamps between the power supply rails. ESD power clamps popularity occurred in the 1990s to achieve better ESD results in semiconductor chips. By the mid-1990s, diode string, metal oxide semiconductor field effect transistor (MOSFET)-based, and bipolar ESD power clamps, and silicon controlled rectifiers (SCRs) became part of the ESD design methodology and practice. From 1995 to 2005, the focus on the MOSFET ESD power clamps has been on producing a better ESD power clamp, design integration, physical placement and low leakage. In the other technologies, the focus has been extending the concepts to triple well complementary metal-oxide semiconductor (CMOS), bipolar and complementary metal oxide semiconductor ...