The ESD Handbook

17ESD in Silicon on Insulator

17.1 Silicon on Insulator (SOI) Technologies

Silicon on insulator (SOI) has become a mainstream technology since the year 2000 [1–69]. Different implementations of SOI have been accepted in the industry. In this chapter, electrostatic discharge (ESD) protection in SOI technology is discussed.

17.1.1 SOI ESD Design Concepts

SOI ESD design is distinct from bulk Complementary Metal-Oxide Semiconductor (CMOS) ESD design as a result of the buried oxide (BOX) film and the metal oxide semiconductor field effect transistor (MOSFET) floating body region [1–69]. The BOX decouples the SOI n-channel and p-channel MOSFET body region from the silicon substrate. The BOX region also separates and isolates the p-channel and n-channel SOI MOSFET. Many of the bulk ESD design practices are similar, but new issues need to be addressed in SOI ESD design. In SOI ESD analysis, active areas include SOI electro-thermal simulation and modeling, experimental work and design integration and SOI patents.

Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. This has led to the need for new semiconductor devices, new ESD design layout, and new circuit innovations.

17.1.2 Distinction of SOI versus Bulk CMOS ESD Structures

Some of the fundamental distinctions are as follows:

• No vertical parasitic devices exist.
• No lateral device ...