The ESD Handbook

19ESD in RF CMOS

19.1 CMOS and ESD

In complementary metal-oxide semiconductor (CMOS) technology, through the 1990s to 2000, the focus of electrostatic discharge (ESD) research was to understand how the evolutionary and revolutionary changes in CMOS influenced ESD robustness and scaling [1–20]. In that time period, technology transitions included high resistance substrates, retrograde implanted wells, shallow trench isolation (STI), silicides, tungsten stud contacts, and copper interconnects to low-k inter-level dielectrics (ILDs).

19.2 RF CMOS

With the migration to radio frequency (RF) CMOS, a few revolutionary changes have occurred in CMOS technology [1–49]. The primary change is metal oxide semiconductor field effect transistor (MOSFET) scaling to thin dielectrics, and small MOSFET channel lengths. With these issues, the MOSFET performance has increased to allow for RF applications to be acceptable in technology.

19.3 RF CMOS and ESD

In RF CMOS, the ESD strategy that is taking place is a function of the application frequency. As the application frequencies are increasing from 1 to 10 GHz, the decisions and choices of usage of ESD, co-synthesis, and the utilization of RF design techniques are taking a greater role. In this chapter, we will review RF ESD device comparison studies, RF ESD design layout choices, and ESD robustness issues with RF passive elements.

19.4 RF CMOS ESD Failure Mechanisms

Table 19.1 contains a brief summary of the ESD mechanisms observed in RF ...