The ESD Handbook

23ESD in Bulk and SOI FINFET

23.1 Early FinFET Structures

Because of the progress in dual gate Silicon on Insulator (DG-SOI) metal oxide semiconductor field effect transistors (MOSFETs), new directions have been taken to move in “surround” gate or “wrap-around” gate structures [1–12]. In 1986, Takahashi et al. [4] proposed the Surround Gate Transistor (SGT) device with the objective of achieving a smaller transistor structure. Hisamoto et al.[5] proposed the Fully Depleted Lean-Channel Transistor (DELTA) device, which was a novel vertical ultra-thin SOI MOSFET structure (Figure 23.1). This evolution has progressed toward a silicon pillar device with a wrap-around gate in both bulk complementary metal-oxide semiconductor (CMOS) and in SOI technology. Tang et al. [10] developed a quasi-planar double-gate device known as a “FinFET.” Concepts of surround gates, wrap-around gates and non-planar dual gates were all different strategies on constructing the non-planar MOSFET into narrow-width silicon pillars leaving the wafer surface to form the 3-D MOSFET structures [1–6].

23.2 FinFET Structure and Design Parameters

In a FinFET structure, the key design parameters are the fin height H, fin thickness, T_si, the effective channel length, L_eff, and the number of parallel fin structures, N_Fin.

Today, these transistors are being demonstrated in 45 nm technology with potential usage in the future. In these structures, the MOSFET gate “wraps around” all sides of the “fin.” Each “fin” is ...