The Essentials of Computer Organization and Architecture, 6th Edition

5.5 INSTRUCTION PIPELINING

By now you should be reasonably familiar with the fetch−decode−execute cycle presented in Chapter 4. Conceptually, each pulse of the computer’s clock is used to control one step in the sequence, but sometimes additional pulses can be used to control smaller details within one step. Some CPUs break down the fetch−decode−execute cycle into smaller steps, where some of these smaller steps can be performed in parallel. This overlapping speeds up execution. This method, used by all current CPUs, is known as pipelining. Instruction pipelining is one method used to exploit instruction-level parallelism (ILP). (Other methods include superscalar and VLIW.) We include it in this chapter because the ISA of a machine affects how ...