Packages and Use Clauses
Packages in VHDL-AMS provide an important way of organizing the data and subprograms declared in a model. In this chapter, we describe the basics of packages and show how they may be used. We also look at several predefined and standard packages, which provide types, natures and operators for use in VHDL-AMS models.
10.1 Package Declarations
A VHDL-AMS package is simply a way of grouping a collection of related declarations that serve a common purpose. They might be a set of subprograms that provide operations on a particular type of data, or they might just be the set of declarations needed to model a particular design. The important thing is that they can be collected together into a separate design ...
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