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The System Designer's Guide to VHDL-AMS by Darrell A. Teegarden, Gregory D. Peterson, Peter J. Ashenden

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chapter eleven

Aliases

Since the main purpose of a model written in VHDL-AMS is to describe a hardware design, it should be made as easy as possible to read and understand. In this chapter, we introduce aliases as a means of making a model clearer. As in everyday use, an alias is simply an alternate name for something. We see how we can use aliases in VHDL-AMS for both data objects and other kinds of items that do not represent data in a model.

11.1 Aliases for Data Objects

If we have a model that includes a data object, such as a constant, a variable, a signal, a quantity, a terminal or, as we see in a later chapter, a file, we can declare an alias for the object with an alias declaration. A simplified syntax rule for this is

An alias ...

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