Before the processor can access a memory location, the Paging Unit must perform two overhead memory reads to access the PDE and a PTE. This can have a severe effect on performance.
When a page is first accessed, the processor performs these two memory reads to obtain the PDE and the selected PTE. To eliminate the need to access this same PTE for future accesses within the same page, IA32 processors incorporate a relatively small, special-purpose cache that keep copies of the most-recently accessed PTEs. The size and organization of this cache can vary from processor to processor.