Eliminating the Directory Lookup
Before the processor can access a memory location, the Paging Unit must perform two overhead memory reads to access the PDE and a PTE. This can have a severe effect on performance.
When a page is first accessed, the processor performs these two memory reads to obtain the PDE and the selected PTE. To eliminate the need to access this same PTE for future accesses within the same page, IA32 processors incorporate a relatively small, special-purpose cache that keep copies of the most-recently accessed PTEs. The size and organization of this cache can vary from processor to processor.
The 386 TLB
The 386 processor incorporated a cache, referred to as a Translation Lookaside Buffer, or TLB. Figure 12-17 on page 235 ...
Get The Unabridged Pentium 4 IA32 Processor Genealogy now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
