Whenever any entity attempts to access an area of memory, there must be a mechanism that ensures that the line that it reads from or writes to is a fresh copy of the line—i.e., it cannot be a stale copy of the line that has not received all updates. The entities that could initiate a memory transaction on the processor FSB are:
The entity that connects the processor to system memory and to the rest of the system. In an earlier PCI system, this would be the North Bridge or the MCH (Memory Control Hub; see Figure 17-1 on page 395). In a PCI Express system, this would be the Root Complex (see Figure 17-2 on page 396).