This section introduces the cache designs most commonly found in IA32 processor implementations.
A fully-associative cache design is comprised of two major elements:
One bank, or Way, of cache SRAM in which the lines of information are stored.
One directory that is used to keep track of where each line originated in memory and what the current state of the line is.
Whenever a memory address is submitted to the cache for a lookup, it is compared to all of the directory entries simultaneously. If there's a match on a valid entry, the cache line in the same relative position in the Way is the desired line. When a new line is fetched from memory, the cache directory is consulted ...