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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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A20 Mask

When the Address Bit 20 Mask (A20M#) input pin is active, the 486 masks physical address bit 20 (A20) before performing a lookup to the internal cache or driving a memory transaction onto the FSB. A20M# emulates the address wraparound at the 1MB boundary that occurs on the 8086/8088. This pin should only be asserted by external logic when the processor is in Real Mode.

Accessing Extended Memory in Real Mode

It is possible to access a small amount of extended memory (memory above 1MB) while in Real Mode. Consider the following example:

mov ax,ffff     ;ffffh to ax
mov ds,ax       ;transfer ffffh to ds
mov al,[0010]   ;transfer contents of memory
                ;location ffff:0010 to al

In order to form the physical memory address to place on the FSB when executing ...

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