The Unabridged Pentium 4 IA32 Processor Genealogy

An Overview of the Pentium^® FSB

Address/Data Bus Structure

Refer to Figure 20-2 on page 471. Although the Pentium® processor implemented a full 32-bit internal address bus, the three least-significant address lines, A[2:0], were not implemented as output pins on the FSB.

Figure 20-2. Pentium® Address/Data Bus Structure

Address Bus Selects Qword

Whenever the processor initiated a transaction on the FSB, logic external to the processor behaved as if the least-significant three address lines were always zero. As a result, the processor could only output addresses divisible by eight. As an example, it could address location 00000100h, but not 00000101h ...