The 4MB feature was first implemented in the Pentium® processor. It was migrated backwards into the later versions of the 486 and is present in all IA32 processor subsequent to the Pentium®.
Enabling 4MB page capability is accomplished by setting CR4[PSE] = 1 (PSE = Page Size Extension; see Figure 21-6 on page 497). 4MB page capability is detected by executing a CPUID request type 1. Bit 3 in EDX = 1 indicates that it is supported (see Figure 21-2 on page 491).
Assume that a task will be accessing a large buffer in memory and that it is the OS's intention that the processor should follow the same rules of conduct when accessing any location(s) in this buffer. As an example, assume it is a 2MB video frame buffer in memory. ...