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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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Local APIC Register Set

The Problem

On pre-Pentium® x86 processors, interrupts from external hardware devices were delivered to the processor on two input pins:

  • INTR. This is the processor's maskable interrupt input. The programmer can disable recognition of this signal line by executing the CLI instruction. This clears EFlags[IF] to 0, masking the INTR input.

  • NMI. This is the processor's Non-Maskable Interrupt input. The programmer cannot mask out recognition of this signal line.

In multiprocessor systems based on the earlier processors, it would have been a mistake for the system board designer to wire the interrupt logic's INTR and NMI outputs to all of the processors. The generation of any interrupt on the INTR or NMI pin would have caused ...

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