The system processor(s) cache information from system memory and may modify the data in the cache but not perform a memory write on the FSB to update the original line in memory. The line in memory is then stale. For this reason, whenever any device (a processor or a device adapter) attempts to access system memory, the memory access must be made visible to the processors so they may snoop the memory address in their caches. In the Snoop Phase of the transaction, the processors provide the request initiator with the snoop result. If the snoop results in a hit on a modified line, the processor with the modified copy of the line asserts the HITM# signal in the Snoop Phase and then provides its modified copy of the line in the transaction's ...

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