O'Reilly logo

The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

Intro to the μop Pipeline

General

While the μop pipeline in the P6 processors consisted of 10 stages, the Pentium® 4 pipeline was completely re-designed and expanded to 20 stages (see Figure 38-22 on page 929). Intel® refers to this as a hyper-pipelined design. The operational processor core clock rate determines how many gates of logic can be included in each pipeline stage. Dividing the core's pipeline into less complex stages with less work performed in each stage (with fewer logic gates) permits a significantly higher core clock frequency.

Figure 38-22. The 20-Stage Instruction Pipeline

While Intel® has provided the names ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required