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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The HT Approach

Instruction Level Parallelism (ILP)

Refer to Figure 39-2 on page 969. Instruction Level Parallelism (ILP) refers to a superscalar processor's ability to dispatch and execute multiple instructions simultaneously (using an array of execution units). Optimized compilers attempt to keep as many of the execution units busy in each clock cycle as possible, but, in almost every clock cycle, one or more execution units are typically idle.

Figure 39-2. It's Difficult Keeping All of the Execution Units Busy

The number of execution units that are actually productive in each clock cycle is a function of the instruction mix that comprises the ...

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