Overview of HT Resource Usage
Refer to Figure 39-6 on page 979. When both logical processors are executing code (i.e., neither is halted) and both require access to the TC, the processor provides interleaved TC access to each logical processor in alternating clock cycles. If one of the logical processors should execute a HLT instruction or does not require access to the TC, the other logical processor has access to the TC in every clock cycle. Although each trace line contains the ID of the logical processor it belongs to, the TC does not impose a constraint on what percentage of the TC can be used by either logical processor.
Figure 39-6. Interleaved Trace Cache Access
A detailed description of the TC can be ...