Hyper-Threading Improved

The 90nm version of the Pentium® 4 processor includes a number of improvements to enhance the performance of the Hyper-Threading feature.

Decreased Possibility of L1 Data Cache Blocking

In the earlier versions of the Pentium® 4 processor, the Data Cache would not block the servicing of load/store requests until four cache misses had occurred. This number has been increased to eight. While this has little effect on a processor executing a single thread, it enhances performance when both logical processors are executing threads (if the threads are accessing different data sets).

Increased the Size of the μop Queue

Refer to Figure 42-3 on page 1107. The size of the μop Queue that feeds the instruction pipeline has been increased ...

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