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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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Everything's Relative

All AGTL+ Signals Are Active When Low

All AGTL+ signal names (e.g., A5#, D63#, BR0#) are followed by the # symbol, indicating that they are in the asserted state when driven low. As a result of this, before the address and data are driven onto the address and data signal lines, they are inverted:

  • An address or data bit that is internally represented by an electrical one is inverted to an electrical zero when it is driven onto its respective address or data signal line.

  • An address or data bit that is internally represented by an electrical zero is inverted to an electrical one when it is driven onto its respective address or data signal line.

Note that data bus inversion may cause some of the 16-bit data groups to be inverted ...

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