The Unabridged Pentium 4 IA32 Processor Genealogy

Guaranteeing the Atomicity of a Read/Modify/Write

This problem came about because processor 1 was able to read the semaphore immediately after processor 0 read it. The two processors were in a race condition. Processor 0 then wrote to it immediately, followed by processor 1 writing to it. The tasks on the two processors each ended up believing it had sole ownership of the buffer.

This problem can be prevented if processor 0 could prevent other initiators from using the FSB from the time it initiates its read until the time it completes the write to update the semaphore to a non-zero value. In other words, it should lock the FSB while it performs the read/modify/write (frequently referred to as a RMW) of the semaphore.

To do this, the programmer ...