The Unabridged Pentium 4 IA32 Processor Genealogy

Chapter 49. Pentium^® 4 FSB Request Phase

The Previous Chapter

This chapter described the mechanism that permits FSB agents to limit the number of transactions that can be injected into the FSB. It included:

• Assert BNR# When One Entry Remains.

• BNR# Can Be Used by a Debug Tool.

• Who Monitors BNR#.

• BNR# is a Shared Signal.

• The Stalled/Throttled/Free Indicator.

• Initial Entry to the Stalled State.

• The Throttled State.

• The Free State.

• As an Agent Approaches Full, It Signals BNR# to Stall Everyone.

• BNR# Behavior at Powerup.

• BNR# Behavior During Runtime.

This Chapter

This chapters provides a detailed description of the Request Phase of a FSB transaction. It includes:

• Introduction to the Request Phase.

• The Source Synchronous Strobes.

• The Request Phase Parity.

• Request ...