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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Response Phase Parity

General

The RS[2:0]# signals are protected by the RSP# parity bit. RSP# is driven in each BCLK cycle of the Response Phase, it must be left high or driven low to force an even number of electrical lows in the overall 4-bit pattern. Note that if the Response Agent stalls the Response Phase (because it doesn't have the response ready to be delivered yet), proper parity must be provided for each Idle response until the actual response is driven.

ChipSet Response Phase Parity Checking and Reporting

Refer to Figure 51-16 on page 1274. The example system shown is a PCI Express-based system and the device that connects the processors to the remainder of the system is referred to as the Root Complex. In a PCI or a PCI-X based ...

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