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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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Example Write To a PCI Express Device

The Write Receives the Defer Response

The previous section, “Example Read From a PCI Express Device” on page 1281, described the actions of the Root Complex upon receipt of a read transaction that targeted a device residing on the PCI bus in Figure 52-2 on page 1279. This section describes the same scenario, but replaces the read with a write transaction.

Refer to Figure 52-5 on page 1290 during this example. Assume that a processor initiates an IO or a memory-mapped IO write transaction that targets the IEEE 1394 FireWire controller on the PCI bus:

  1. The write request is issued by the processor in BCLK cycle 1. The Root Complex latches the address and transaction type in Packet A and the Deferred ID (consisting ...

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