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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Interrupt Acknowledge Transaction

Background

An IA32-based system incorporates an interrupt controller that receives interrupt requests from IO devices and passes them on to the processor (or to the processor cluster). The interrupt controller will either consist of a pair of cascaded 8259A's in a single processor system (see “Before the Advent of the APIC” on page 1498), or an IO APIC module in a multiprocessor system.

Refer to Figure 54-1 on page 1304. In earlier chipsets, the interrupt controller was incorporated in the South Bridge. It is found in the ICH (the IO Control Hub) in the chipsets that are prevalent as of this writing. This is a strategically convenient place for it because the interrupt requests from PCI and legacy ISA targets ...

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