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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The BTM Transaction Is Used for Program Debug

The Problem

Before processors had internal caches, every memory read and write was performed on the FSB. With a bus analyzer, you could therefore see every instruction that was fetched from memory for decode and execution. You could see when a branch instruction was fetched and, when it was subsequently decoded and executed, you would see the processor alter its program flow when the processor began to issue memory read requests starting at the branch target address. In other words, you had full visibility to watch your program being executed.

Refer to Figure 54-3 on page 1310. When a processor incorporates an internal cache, however, program execution tracing becomes a real problem. After it reads ...

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