The MSRs
Table 56-2 on page 1347 identifies the MSRs implemented in the Pentium® 4 and Pentium® M processors. Starting with the Pentium® 4, all MSRs in the table with shaded register names (and starting with “IA32_”) are defined as part of the IA32 architecture and, as such, are guaranteed to be implemented at the same MSR addresses in future IA32 processors.
| ECX = Reg Address before executing RDMSR or WRMSR) | Register Name | 1st in | Description | |
| Hex | Decimal | |||
| Miscellaneous MSRs | ||||
| 000h | 0 | IA32_P5_MC_ADDR | P5 | Please note that, although these are Pentium®-specific MSRs, access attempts in all post-Pentium® processors do not cause an exception. |
| 001h | 1 | IA32_P5_MC_TYPE | ||
| 010h | 16 | IA32_TSC | The Time Stamp Counter (TSC) register was introduced ... | |
Get The Unabridged Pentium 4 IA32 Processor Genealogy now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
