The MSRs

Table 56-2 on page 1347 identifies the MSRs implemented in the Pentium® 4 and Pentium® M processors. Starting with the Pentium® 4, all MSRs in the table with shaded register names (and starting with “IA32_”) are defined as part of the IA32 architecture and, as such, are guaranteed to be implemented at the same MSR addresses in future IA32 processors.

Table 56-2. Pentium® 4 and Pentium® M MSRs
ECX = Reg Address before executing RDMSR or WRMSR)Register Name1st inDescription
Miscellaneous MSRs
000h0IA32_P5_MC_ADDRP5Please note that, although these are Pentium®-specific MSRs, access attempts in all post-Pentium® processors do not cause an exception.
010h16IA32_TSCThe Time Stamp Counter (TSC) register was introduced ...

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