The last instruction executed in the SM handler is the Resume (RSM) instruction. Its execution causes the processor to reload its register set from the State Save Area (see Figure 60-1 on page 1470 and Table 60-1 on page 1471) before resuming execution of the program that was interrupted by the chipset's generation of an SMI to the processor.
If any reserved bits in CR4 are set to 1.
If there is any illegal combination of bits in CR0 (e.g., Paging enabled and Protected Mode disabled, or NW = 1 and CD = 0).
On the Pentium® ...