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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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Entering SMM

The SMI Interrupt Is Generated

The chipset causes the processor to enter SMM by generating an SMI# to the processor. The processor recognizes the interrupt on the next instruction boundary.

No Interruptions Please

General

When the SMI is recognized by the processor, the processor saves the processor's register set to the State Save Area before proceeding. The processor does not recognize any hardware interrupts during the State Save operation. Once the register set has been saved, the processor disables all hardware interrupts in the following manner:

  • EFlags[IF] is cleared to 0, disabling the processor's ability to recognize external hardware interrupts delivered on the INTR (i.e., LINT0) input (or by the delivery of an IPI to the ...

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