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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Local APIC Register Set

Local and IO APIC Register Areas Are Uncacheable

As with all areas of memory populated by memory-mapped IO registers, the memory areas within which the Local and IO APIC's register sets reside must be designated as uncacheable (UC) memory in the MTRRs.

Introduction to the Local APIC's Register Set

Figure 61-16 on page 1525 illustrates the Local APIC's memory-mapped IO register set. In the Pentium® processor, the register set occupied a 4KB memory address range starting at location FEE00000h and the address range could not be altered. This constraint disappeared with the addition of the APIC_BASE MSR (see Figure 61-15 on page 1524; referred to as the IA32_APIC_BASE register starting with the Pentium® 4) in the Pentium® ...

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