Three-dimensional Integrated Circuit Design

Appendix D. Proof of Condition for Via Placement of Multiterminal Nets

In this appendix, a proof for necessary condition 1 is provided.

Condition 1: If r^j > r^j+1, only a type-1 move for v^j can reduce the delay of a tree.

Proof: Consider Fig D-1 where the interplane via v^j (the solid square) can be placed in any direction d^e, d^s, and dⁿ within the interval l^de, l^ds, and l^dn, respectively. For the tree shown in Fig. D-1 and removing the terms that are independent of v^j, (8-1) is (D-1)

Figure Figure D-1. A portion of an interconnect tree.

where ...