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Three-dimensional Integrated Circuit Design by Eby G. Friedman, Vasilis F. Pavlidis

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Appendix D. Proof of Condition for Via Placement of Multiterminal Nets

In this appendix, a proof for necessary condition 1 is provided.

Condition 1: If rj > rj+1, only a type-1 move for vj can reduce the delay of a tree.

Proof: Consider Fig D-1 where the interplane via vj (the solid square) can be placed in any direction de, ds, and dn within the interval lde, lds, and ldn, respectively. For the tree shown in Fig. D-1 and removing the terms that are independent of vj, (8-1) is (D-1)

Figure Figure D-1. A portion of an interconnect tree.

where ...

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