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Three-Dimensional Integrated Circuit Design, 2nd Edition

Book Description

Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.

Expanded with new chapters and updates throughout based on the latest research in 3-D integration:

  • Manufacturing techniques for 3-D ICs with TSVs
  • Electrical modeling and closed-form expressions of through silicon vias
  • Substrate noise coupling in heterogeneous 3-D ICs
  • Design of 3-D ICs with inductive links
  • Synchronization in 3-D ICs
  • Variation effects on 3-D ICs
  • Correlation of WID variations for intra-tier buffers and wires
  • Offers practical guidance on designing 3-D heterogeneous systems
  • Provides power delivery of 3-D ICs
  • Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more
  • Provides experimental case studies in power delivery, synchronization, and thermal characterization

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Dedication
  6. List of Figures
  7. About the Authors
  8. Preface to the Second Edition
  9. Preface to the First Edition
  10. Acknowledgments
  11. Organization of the Book
  12. Chapter 1. Introduction
    1. Abstract
    2. 1.1 Interconnect Issues in Integrated Systems
    3. 1.2 Three-Dimensional or Vertical Integration
    4. 1.3 Book Organization
  13. Chapter 2. Manufacturing of Three-Dimensional Packaged Systems
    1. Abstract
    2. 2.1 Stacking Methods for Transistors, Circuits, and Dies
    3. 2.2 System-on-Package
    4. 2.3 Technologies for System-in-Package
    5. 2.4 Technologies for 2.5-D Integration
    6. 2.5 Summary
  14. Chapter 3. Manufacturing Technologies for Three-Dimensional Integrated Circuits
    1. Abstract
    2. 3.1 Monolithic Three-Dimensional ICs
    3. 3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via
    4. 3.3 Contactless Three-Dimensional ICs
    5. 3.4 Vertical Interconnects for Three-Dimensional ICs
    6. 3.5 Summary
  15. Chapter 4. Electrical Properties of Through Silicon Vias
    1. Abstract
    2. 4.1 Physical Characteristics of a Through Silicon Via
    3. 4.2 Electrical Model of Through Silicon Via
    4. 4.3 Modeling a Three-Dimensional Via as a Cylinder
    5. 4.4 Compact Models
    6. 4.5 Through Silicon Via Impedance Models
    7. 4.6 Electrical Characterization Through Numerical Simulation
    8. 4.7 Case Study—Through Silicon Via Characterization of the MITLL TSV process
    9. 4.8 Summary
  16. Chapter 5. Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs
    1. Abstract
    2. 5.1 Heterogeneous Substrate Coupling
    3. 5.2 Frequency Response
    4. 5.3 Techniques to Improve Noise Isolation
    5. 5.4 Summary
  17. Chapter 6. Three-Dimensional ICs with Inductive Links
    1. Abstract
    2. 6.1 Wireless On-Chip Communication Interfaces
    3. 6.2 On-Chip Inductors for Intertier Links
    4. 6.3 Transmitter and Receiver Circuits
    5. 6.4 Challenges for Wireless On-Chip Communication
    6. 6.5 Intertier Power Transfer
    7. 6.6 Summary
  18. Chapter 7. Interconnect Prediction Models
    1. Abstract
    2. 7.1 Interconnect Prediction Models for Two-Dimensional Circuits
    3. 7.2 Interconnect Prediction Models for Three-Dimensional ICs
    4. 7.3 Projections for Three-Dimensional ICs
    5. 7.4 Summary
  19. Chapter 8. Cost Considerations for Three-Dimensional Integration
    1. Abstract
    2. 8.1 Through Silicon Via Processing Options
    3. 8.2 Interposer-Based Systems Integration
    4. 8.3 Comparison of Processing Cost for 2.5-D and Three-Dimensional Integration
    5. 8.4 Summary
  20. Chapter 9. Physical Design Techniques for Three-Dimensional ICs
    1. Abstract
    2. 9.1 Floorplanning Techniques
    3. 9.2 Floorplanning Three-Dimensional ICs
    4. 9.3 Placement Techniques
    5. 9.4 Placement in Three-Dimensional ICs
    6. 9.5 Routing Techniques
    7. 9.6 Layout Tools
    8. 9.7 Summary
  21. Chapter 10. Timing Optimization for Two-Terminal Interconnects
    1. Abstract
    2. 10.1 Intertier Interconnect Models
    3. 10.2 Two-Terminal Nets With a Single Intertier Via
    4. 10.3 Two Terminal Interconnects With Multiple Intertier Vias
    5. 10.4 Summary
  22. Chapter 11. Timing Optimization for Multiterminal Interconnects
    1. Abstract
    2. 11.1 Timing Driven Via Placement for Intertier Interconnect Trees
    3. 11.2 Multiterminal Interconnect Via Placement Heuristics
    4. 11.3 Via Placement Algorithms for Interconnect Trees
    5. 11.4 Discussion of Via Placement Results
    6. 11.5 Summary
  23. Chapter 12. Thermal Modeling and Analysis
    1. Abstract
    2. 12.1 Heat Transfer in Three-Dimensional ICs
    3. 12.2 Closed-Form Temperature Models
    4. 12.3 Mesh-Based Thermal Models
    5. 12.4 Thermal Analysis Techniques
    6. 12.5 Summary
  24. Chapter 13. Thermal Management Strategies for Three-Dimensional ICs
    1. Abstract
    2. 13.1 Thermal Management Through Power Density Reduction
    3. 13.2 Thermal Management Through Enhanced Thermal Conductivity
    4. 13.3 Hybrid Methodologies for Thermal Management
    5. 13.4 Summary
  25. Chapter 14. Case Study: Thermal Coupling in 3-D Integrated Circuits
    1. Abstract
    2. 14.1 Thermal Propagation Test Circuit
    3. 14.2 Setup and Experiments
    4. 14.3 Design Considerations Based on Experimental Results
    5. 14.4 Verification of Experimental Results with Simulations
    6. 14.5 Summary
  26. Chapter 15. Synchronization in Three-Dimensional ICs
    1. Abstract
    2. 15.1 Synthesis Techniques for Planar Clock Distribution Networks
    3. 15.2 Global Three-Dimensional Clock Distribution Networks
    4. 15.3 Synthesis of Three-Dimensional Clock Distribution Networks
    5. 15.4 Practical Considerations of Three-Dimensional Clock Tree Synthesis
    6. 15.5 Summary
  27. Chapter 16. Case Study: Clock Distribution Networks for Three-Dimensional ICs
    1. Abstract
    2. 16.1 MIT Lincoln Laboratories Three-Dimensional IC Fabrication Technology
    3. 16.2 Three-Dimensional Test Circuit Architecture
    4. 16.3 Clock Distribution Network Structures Within the Test Circuit
    5. 16.4 Models of the Clock Distribution Network Topologies Incorporating Three-Dimensional Via Impedance
    6. 16.5 Experimental Results
    7. 16.6 Summary
  28. Chapter 17. Variability Issues in Three-Dimensional ICs
    1. Abstract
    2. 17.1 Process Variations in Data paths Within Three-Dimensional ICs
    3. 17.2 Effects of Process Variations on Clock Paths
    4. 17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks
    5. 17.4 Summary
  29. Chapter 18. Power Delivery for Three-Dimensional ICs
    1. Abstract
    2. 18.1 The Power Delivery Challenge
    3. 18.2 Models for Three-Dimensional Power Distribution Networks
    4. 18.3 Through Silicon Via Technologies to Mitigate Power Supply Noise
    5. 18.4 Decoupling Capacitance for Three-Dimensional Power Distribution Networks
    6. 18.5 Wire Sizing Methods in Three-Dimensional Power Distribution Networks
    7. 18.6 Summary
  30. Chapter 19. Case Study: 3-D Power Distribution Topologies and Models
    1. Abstract
    2. 19.1 3-D Power Distribution Network Test Circuit
    3. 19.2 Experimental Results
    4. 19.3 Characteristics of 3-D Power Distribution Topologies
    5. 19.4 Summary
  31. Chapter 20. 3-D Circuit Architectures
    1. Abstract
    2. 20.1 Classification of Wire Limited 3-D Circuits
    3. 20.2 3-D Microprocessors and Memories
    4. 20.3 3-D Networks-on-Chip
    5. 20.4 3-D FPGAs
    6. 20.5 Summary
  32. Chapter 21. Conclusions
  33. Appendix A. Enumeration of Gate Pairs in a 3-D IC
  34. Appendix B. Formal Proof of Optimum Single Via Placement
  35. Appendix C. Proof of the Two-Terminal Via Placement Heuristic
  36. Appendix D. Proof of Condition for Via Placement of Multi-terminal Nets
  37. Appendix E. Correlation of WID Variations for Intratier Buffers
  38. Appendix F. Extension of the Proposed Model to Include Variations of Wires
  39. Glossary of Terms
  40. References
  41. Index