Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs*
Abstract
The effects of through silicon vias (TSVs) on the noise characteristics of the substrates within the tiers are described in this chapter. The noise due to different types of substrates is discussed and appropriate noise models for each type of substrate are offered. Mitigation techniques to suppress the noise from the TSVs are also discussed. The frequency response for a wide range of frequencies is evaluated as some of the tiers in a three-dimensional stack can include high frequency circuits, such as detectors and RF circuits. Different substrate materials including gallium arsenide (GaAs), germanium (Ge), and mercury cadmium telluride (HgCdTe) are considered. ...
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