Three-Dimensional Integrated Circuit Design, 2nd Edition

Chapter 11

Timing Optimization for Multiterminal Interconnects*

Abstract

The problem of timing driven placement for multipin intertier nets is discussed in this chapter. Near-optimal heuristics based on the Elmore delay are provided to solve this problem. These heuristics target different timing optimization objectives for intertier nets, such as minimizing the maximum sink delay or the sum of the sink delays. The efficiency of these placement heuristics is evaluated on several benchmark nets for three-dimensional circuits with different number of tiers. The effect of the available whitespace for improving the overall delay of multipin intertier nets by carefully placing the through silicon vias is presented.

Keywords

3-D net timing optimization; ...