Synchronization in Three-Dimensional ICs
Abstract
The important issue of synchronization is the topic of this chapter. Clock tree synthesis (CTS) techniques under diverse design objectives for multi-tier systems are described. As these techniques extend CTS methods for planar circuits to three-dimensional (3-D) structures, standard algorithms and methods used in the synthesis of planar clock trees are presented. These techniques include the method of means and medians and the deferred-merge embedding method. A review of global clock distribution networks for 3-D circuits follows. Synthesis techniques for 3-D clock trees are extensively described. The last part of this chapter is dedicated to practical issues in the CTS process for 3-D ...
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