Variability Issues in Three-Dimensional ICs*
Abstract
The effects of variations on the behavior of three-dimensional (3-D) circuits are reviewed in this chapter. Stochastic models that describe the performance variability of 3-D circuits are presented. Both interdie and intradie variations are considered. Detailed analytic models to describe the combined effects of die-to-die and within-die variations for clock paths that span more than one tier are included. The distribution of clock skew for different clock networks is evaluated based on this model, and enhanced topologies that reduce skew variability are presented. The skew model is extended to include power supply noise, and design guidelines for clock trees considering both power ...
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