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Top-Down Digital VLSI Design by Hubert Kaeslin

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3.7.6 Pipeline interleaving, not quite an equivalence transform

It has repeatedly been noted in this section that any attempt to insert an extra register into a feedback loop with the idea of pipelining the datapath destroys the equivalence between original and pipelined computations unless its effect is somehow compensated. After all, circuits c and b of fig.3.41 behave differently. Although this may appear a futile question, let us ask

“What happens if we do just that to a first-order recursion?”

Adding an extra latency register to (3.69) results in the DDG of fig.3.42a and yields

y(k)=f(y(k-2),x(k))

si107_e  (3.73)

Figure 3.42 Pipeline interleaving. ...

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