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Top-Down Digital VLSI Design by Hubert Kaeslin

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Chapter 7

Clocking of Synchronous Circuits

Abstract

In theory, all flip-flops and memories in a clock domain update their state at the same time. Reality is different due to two real-world phenomena that cause clock edges to get scattered over time. Numerous schemes for driving synchronous digital circuits have been devised over the years. Some of them are more vulnerable to clock skew and jitter than others, each asks for somewhat different hardware resources, and not all of them have the same impact on performance. A total of six clocking disciplines are introduced and evaluated from a VLSI perspective. Another important topic are clock distribution networks such as clock trees and grids designed to minimize skew. Also discussed are techniques ...

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