Understanding IBM eServer pSeries Performance and Sizing

© Copyright IBM Corp. 2001 39

Chapter 3. IBM RS/6000 and IBM pSeries architectures

In February 1990, IBM introduced the first RISC System/6000 (RS/6000) with

the first Performance Optimization With Enhanced RISC (POWER)

architecture. Since that date, several POWER architectures have been

designed for the RS/6000 models.

In 1991, with the alliance of Apple and Motorola, IBM started a plan for the

future that would span a range from the small, battery-operated computer to

very large supercomputers and mainframes. The PowerPC family of

microprocessors, a single-chip implementation jointly developed by Apple,

IBM, and Motorola, established a rapidly expanding market for RISC-based

hardware and software. IBM has several successful lines of PowerPC-based

products for workstations and servers. Motorola introduced a broad range of

desktop and server systems, and other companies such as Bull, Canon, and

FirePower have announced or shipped PowerPC-based systems. Apple has

Power Macintosh systems, and companies such as Daystar, Pioneer, Power

Computing, and Radius also have announced Power Macintosh-compatible

systems.

With these successes the alliance ended, leaving IBM to continue building on

it’s CPU architecture and design, which can be seen with the introduction of

the powerful copper technology deployed in the S80 servers.

3.1 POWER2 Super Chip

In October 1996, IBM announced the RS/6000 Model 595. This was the first

machine to be based on the POWER2 Super Chip (P2SC) processor. As its

name suggests, this is a single chip implementation of the POWER2

architecture, enabling the clock speed to be increased further. Currently the

P2SC processors are employed only in the RS/6000 SP Thin4 nodes, where

they run at clock speed of 160 MHz with a theoretical peak speed of 640

MFLOPS.

The POWER2 Super Chip (P2SC) is a compression of the POWER2

eight-chip architecture into a single chip with increased processor speed and

performance. It retains the design of its predecessor, the POWER2.

The initial models had clock speeds of 120 MHz and 135 MHz. High-density

CMOS-6S technology allows each to incorporate 15,000,000 transistors.

40 RS/6000 and IBM ^ pSeries Performance and Sizing

The most significant change is a halving of the size of the data cache and the

data TLB, which now are 128 KB and 256 KB, respectively. These changes

were required to fit the eight-chip processor onto a single chip.

The P2SC delivers the processing and dual floating-point power needed for

large, numeric-intensive tasks as well as the integer and transaction

performance for commercial applications. The P2SC contains on-chip 32 KB

instruction cache and 128 KB data cache, and is full binary compatible with

the POWER2 architecture

SP2 Thin nodes are the only current systems that use the POWER2 chips.

Figure 12. POWER2 Super Chip Module

DCUDCU

DCU

DCU

128 KB D Cache

Other word = 32 bits

Eight words

Memory Data Bus

SIO

Tw o

words

Sync

Two FXU Data Buses

One word

ICU

PBUS

One word

SCU

FXU

FPU

Instruction Dispatch Bus

Four words

ICache Raised Bus

Four words

Single Chip

Two FPU Data Buses

Four words