Verification Techniques for System-Level Design

Chapter 2. Higher-Level Design Methodology and Associated Verification Problems

Introduction

This chapter introduces high-level design methodologies that deal with design processes higher than register transfer level (RTL). The intention is to present the key issues in high-level designs that are related to design verification. Logic synthesis and layout synthesis are now widely used, and most of the design activities from RTL can be automated with CAD tools. In design stages higher than RTL, however, design supports are only now in an introductory phase. Various C-based design and specification languages have been developed, and associated design methodologies have been proposed. They start with C descriptions that are programming-language-like ...